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M37754FFCGP Datasheet, PDF (58/68 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
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MITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Bus timing data formulas
Memory expansion and Microprocessor mode : High-speed running (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) ≤ 40 MHz when
the clock source select bit = “0”∗, unless otherwise noted)
Symbol
Parameter
3-φ access 4-φ access 5-φ access Unit
tsu(A–DL/DH) Data setup time with address stabilized
tsu(CS–DL/DH) Data setup time with chip select stabilized
tw(φH), tw(φL) φ high-level pulse width, φ low-level pulse width
__
__
___ ___
tw(WR), tw(RD) WR, RD low-level pulse width
td(A–WR)
Address output delay time
td(A–RD)
Address output delay time
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
Address output delay time
____
BHE outuput delay time
____
BHE outuput delay time
____
BHE outuput delay time
td(CS–WR)
Chip select output delay time
td(CS–RD)
Chip select output delay time
td(CS–ALE)
Chip select output delay time
tw(ALE)
ALE pulse width
th(WR–A)
Address hold time
th(RD–A)
td(WR–BHE)
td(RD–BHE)
Address hold time
____
BHE hold time
____
BHE hold time
td(WR–CS)
Chip select hold time
td(RD–CS)
Chip select hold time
th(WR–DLQ/DHQ) Data hold time
tpxz(WR–DLZ/DHZ) Floating start delay time
tsu(LA–DL)
Data setup time with address stabilized
td(LA–WR)
Address outuput delay time
td(LA–RD)
Address outuput delay time
td(LA–ALE)
Address outuput delay time
td(ALE–LA)
Address hold time
tpzx(RD–DLZ) Floating release delay time
V: f(XIN) ≤ 20 MHz when the clock source select bit = “1”
Note: When the clock source select bit is “1”, regard f(XIN) in tables as 2·f(XIN).
5 × 109
f(XIN)
– 60
7 × 109
f(XIN)
– 65
9 × 109
f(XIN)
– 65
ns
5 × 109
f(XIN)
– 60
7 × 109
f(XIN)
– 65
9 × 109
f(XIN)
– 65
ns
1 × 109
f(XIN)
– 20
ns
3 × 109
f(XIN)
– 20
4 × 109
f(XIN)
– 20
6 × 109
f(XIN)
– 20
ns
2 × 109
f(XIN)
– 25
3 × 109
f(XIN)
– 30
ns
2 × 109
f(XIN)
– 25
3 × 109
f(XIN)
– 30
ns
1 × 109
f(XIN)
– 15
2 × 109
f(XIN)
– 15
ns
2 × 109
f(XIN)
– 25
3 × 109
f(XIN)
– 30
ns
2 × 109
f(XIN)
– 25
3 × 109
f(XIN)
– 30
ns
1 × 109
f(XIN)
– 15
2 × 109
f(XIN)
– 15
ns
2 × 109
f(XIN)
– 25
3 × 109
f(XIN)
– 30
ns
2 × 109
f(XIN)
– 25
3 × 109
f(XIN)
– 30
ns
1 × 109
f(XIN)
– 15
2 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
2 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 10
ns
1 × 109
f(XIN)
+5
ns
5 × 109
f(XIN)
– 75
7 × 109
f(XIN)
– 75
9 × 109
f(XIN)
– 75
ns
2 × 109
f(XIN)
– 35
3 × 109
f(XIN)
– 35
ns
2 × 109
f(XIN)
– 35
3 × 109
f(XIN)
– 35
ns
1 × 109
f(XIN)
– 20
2 × 109
f(XIN)
– 20
ns
1 × 109
f(XIN)
– 15
ns
1 × 109
f(XIN)
– 10
ns
58
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