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M37754FFCGP Datasheet, PDF (21/68 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
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MITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Erase command
The erase command is executed by inputting command code 2016
in the first cycle and command code 2016 again in the second cycle.
The command code is latched into the internal command latch at the
___
rising edges of the WE input in the first cycle and in the second cycle,
respectively. The erase operation is initiated at the rising edge of the
___
WE input in the second cycle, and the memory contents are collec-
tively erased within 9.5 ms as measured by the internal timer. Note
that data 0016 must be written to all memory locations before execut-
ing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the fail-
ure is found in this verification, the user must repeatedly ex-
ecute the erase command until the pass. Refer to Figure 12
for the erase flowchart.
Erase verify command
The user must verify the contents of all addresses after completing
the erase command. The microcomputer enters the erase verify
mode by inputting the verify address and command code A016 in the
first cycle. The address is internally latched at the falling edge of the
___
WE input, and the command code is internally latched at the rising
___
edge of the WE input. When control signals are input in the second
cycle at the timing shown in Figure 11, the M37754FFCGP and the
M37754FFCHP output the contents of the specified address to the
external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the op-
eration of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
VIH
Address
VIL
VIH
CE
VIL
VIH
OE
VIL
VIH
WE
VIL
VIH
Data
VIL
VPPH
VPP
VPPL
Erase
Verify
address
Erase verify
tWC
tAS tAH
tCS
tCS
tCH
tCH
tCS
tCH
tRRW
tWP
tWPH
tWP
tDE
tWP
tWRR
tVSC
tDS
2016
tDH
tDS
2016
tDH
tDS
A016
tDH
Dout
Verify data output
Fig. 11 Input/output timings during erasing (Verify data is output at the same timing as for read.)
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