M37754FFCGP Datasheet, PDF (32/68 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

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MITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Flash memory mode-3 (CPU reprogramming
mode)
The M37754FFCGP and the M37754FFCHP have the CPU repro-
gramming mode where a built-in flash memory is handled by the cen-
tral processing unit (CPU). 112 Kbytes (addresses 00100016 to
00EFFF16 and addresses 01100016 to 01EFFF16) of the 120-Kbyte
flash memory shown in Figure 1 can be reprogrammed (erase and
program). Remaining 8 Kbytes of the flash memory (addresses
00F00016 to 010FFF16) cannot be reprogrammed, but can be read.
(It is possible to reprogram this remaining 8 Kbytes in the parallel I/O
mode and the serial I/O mode). This area of 8 Kbytes can be used as
an area where the control program of CPU reprogramming mode is
stored.
In CPU reprogramming mode, the flash memory is handled by writ-
ing and reading to/from the flash memory control register (see Fig-
ure 21) and the flash command register (see Figure 22).
The CNVSS pin is used as the VPP power supply pin in CPU repro-
gramming mode. It is necessary to apply the power-supply voltage of
VPPH from the external to this pin.
Functional outline (Parallel input/output
mode)
Figure 21 shows the flash memory control register bit configuration.
Figure 22 shows the flash command register bit configuration.
Bit 0 of the flash memory control register is the CPU reprogramming
mode select bit. When this bit is set to “1” and VPPH is applied to the
CNVss/VPP pin, the CPU reprogramming mode is selected. Whether
the CPU reprogramming mode is realized or not is judged by reading
the CPU reprogramming mode monitor flag (bit 3 of the flash
memory control register).
Bit 1 is a busy flag which becomes “1" during auto erase, erase, and
program execution.
Whether these operations have been completed or not is judged by
checking this flag after each command of auto erase, erase, and the
program is executed.
Bits 4, 5 of the flash memory control register are the erase/program
area select bits. These bits specify an area where auto erase, erase,
and program is operated. When the auto erase and the erase com-
mands are executed after an area is specified by these bits, only the
specified area is erased. Only for the specified area, programming is
enabled; for the other areas, programming is disabled.
Figure 23 shows the processor mode register 0 bit configuration in
the CPU reprogramming mode. Set bit 1 to “0” (single-chip or
memory expansion mode) in the CPU reprogramming mode. Set bit
2 (internal memory access bus cycle select bit) to “0.”
Be sure to set data length select flag m to “1" (8-bit length) before-
hand because writing and reading of data are operated in unit of
byte.
76543210
0
0
Address
Flash memory control regsiter 6716
CPU reprogramming mode select bit (Notes 1, 2)
0 : CPU reprogramming mdoe is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Auto erase/Erase/Program busy flag
0 : Auto erase, erase, and program are completed or not have been executed.
1 : Auto erase/erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Fix this bit to “0.”
Erase/Program area select bits
0 ! : Addresses 00100016 to 00EFFF16
and addresses 01100016 to 01EFFF16 (total 112 Kbytes)
1 0 : Addresses 00100016 to 00EFFF16 (total 56 Kbytes)
1 1 : Addresses 01100016 to 01EFFF16 (total 56 Kbytes)
Fix this bit to “0.”
Notes 1: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
2: When bit 0 is “1,” the processor mode does not change even if VPPH is applied to the CNVSS/VPP pin.
Fig. 21 Flash memory control register bit configuration
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