M37754FFCGP Datasheet, PDF (57/68 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

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ITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit =
“0”^∗, unless otherwise noted)
Memory expansion and Microprocessor mode : High-speed running
Symbol
Parameter
3-φ access 4−φ access 5-φ access
Min. Max. Min. Max. Min. Max. ^Unit
tw(φH), tw(φL)
td(φ1–WR)
td(φ1–RD)
__
tw(WR)
__
tw(RD)
φ high-level pulse width, φ low-level pulse width
___
WR output delay time
___
RD output delay time
___
WR low-level pulse width
___
RD low-level pulse width
(Note) 5
5
5
ns
–7 12 –7 12 –7 12 ns
–7 12 –7 12 –7 12 ns
(Note) 55
80
130
ns
(Note) 55
80
130
ns
td(A–WR)
Address output delay time
(Note) 25
45
45
ns
td(A–RD)
Address output delay time
(Note) 25
45
45
ns
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
Address output delay time
____
BHE output delay time
____
BHE output delay time
____
BHE output delay time
(Note) 10
35
35
ns
(Note) 25
45
45
ns
(Note) 25
45
45
ns
(Note) 10
35
35
ns
td(CS–WR)
Chip select output delay time
(Note) 25
45
45
ns
td(CS–RD)
Chip select output delay time
(Note) 25
45
45
ns
td(CS–ALE)
Chip select output delay time
(Note) 10
35
35
ns
td(WR–DLQ/DHQ) Data output delay time
35
35
35 ns
tpxz(WR–DLZ/DHZ) Floating start delay time
(Note)
30
30
30 ns
td(ALE–WR)
ALE output delay time
4
4
4
ns
td(ALE–RD)
ALE output delay time
4
4
4
ns
tw(ALE)
ALE pulse width
(Note) 10
35
35
ns
th(WR–A)
Address hold time
(Note) 10
10
10
ns
th(RD–A)
th(WR–BHE)
th(RD–BHE)
Address hold time
____
BHE hold time
____
BHE hold time
(Note) 10
10
10
ns
(Note) 10
10
10
ns
(Note) 10
10
10
ns
th(WR–CS)
Chip select hold time
(Note) 10
10
10
ns
th(RD–CS)
Chip select hold time
(Note) 10
10
10
ns
th(WR–DLQ/DHQ)
Data hold time
(Note) 15
15
15
ns
tpzx(WR–DLZ/DHZ) Floating release delay time
0
0
0
ns
td(LA–WR)
Address output delay time
(Note) 15
40
40
ns
td(LA–RD)
Address output delay time
(Note) 15
40
40
ns
td(LA–ALE)
Address output delay time
(Note) 5
30
30
ns
th(ALE–LA)
Address hold time
(Note) 10
10
10
ns
tPXZ(RD–DLZ)
Floating start delay time
5
5
5
ns
tPZX(RD–DLZ)
Floating release delay time
(Note) 15
15
15
ns
td(WR–PiQ)
Port Pi data output delay time (i = 4—9, 11)
60
60
60 ns
∗^{: f(XIN) = 20 MHz when the clock source selet bit = “1”}
Note: Since the values depend on external clock frequency f(XIN), calculate them by using the bus timing data formulas on the next page.
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