GP2021 Datasheet, PDF (7/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
Difference between Real and Complex_Input
Mode
The input mode is selected by theFRONT_END_MODE bit
in the SYSTEM_SETUP register. It defaults to Real_Input
mode at power up. The differences between Real and
Complex input mode are summarised in the following table.
Description
Real_Input mode
Complex_Input mode
Recommended Master clock frequency
40MHz
35MHz
GP2021 internal clocking ¹
±7
÷6
MICRO_CLK 2 output frequency
mark : space
20MHz
1:1
17.5MHz
1:1
Pin No 76
SIGN 0
SIGN_I
Pin No 77
MAG 0
MAG_I
Pin No 78
SIGN 1
SIGN_Q
Pin No 79
MAG 1
MAG_Q
Input Signal Sampling Rate
5.714MHz
5.833MHz
SAMPCLK output frequency
5.714MHz
Not available
mark : space
4:3
(held Low)
)
Notes. 1 The GP2021 interrupt and TIC timebase dividers are clocked by this resulting clock.
2 The MCLK output is derived from this signal. In ARM mode the phases of MCLK are stretched by the
Microprocessor Interface block.
FUNCTIONAL DESCRIPTION
The GP2021 incorporates a 12 Channel GPS Correlator,
together with microprocessor support functions including a
Dual UART, a Real Time Clock and Memory Control Logic for
the ARM60 microprocessor. It can be configured for either
ARM System mode or Standard Interface mode. A block
diagram of the GP2021 is shown in Fig. 3.
Whilst in ARM System mode the Memory Control Logic
allows an ARM60 microprocessor to interface with the
Correlator, Real Time Clock, Dual UART and a variety of
memory devices (i.e.
SRAM, EPROM, Flash and EEPROM), without the need for
external glue logic.
In Standard Interface mode the GP2021 allows most 16
and 32 bit microprocessors to interface with the Correlator,
Real Time Clock and Dual UART. More specifically, this mode
allows the interface to be configured for either Intel or Motorola
style microprocessor interfaces.
In the functional description which follows the correlator is
described first, followed by the peripheral functions.
SIGN, MAG
SAMPCLK
CLK_T, CLK_I
POWER_GOOD
PLL_LOCK
12 CHANNEL
GPS
CORRELATOR
MICRO_CLK
POWER &
RESET
CONTROL
DUAL UART
REAL – TIME
CLOCK
CONTROL BUS
DATA BUS
MICROPROCESSOR INTERFACE
ARM SYSTEM
STANDARD
INTERFACE
NARMSYS
A<9:0>
NINTELMOT
WRPROG
Fig. 3 : GP2021 block diagram
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