GP2021 Datasheet, PDF (23/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

to instigate this operation. The reading of measurement data
can be either interrupt driven or polled. For the interrupt driven
method the microprocessor reads the ACCUM_STATUS_B
or MEAS_STATUS_A register after each MEAS_INT, and if
the TIC bit is set, subsequently reads the Measurement data.
For the polled method the ACCUM_STATUS_A register is
always read following every ACCUM_INT. In addition the
ACCUM_STATUS_B register is read on each ACCUM_INT to
ensure no Accumulated Data has been missed and to check
the TIC bit (along with several other status bits). The software
tests the TIC bit to determine if new Measurement Data is
available to be read.
Preset Mode
Each channel can be programmed into PRESET mode
by writing a High into the PRESET/UPDATEB bit of the
CHx_SATCNTL register.
When a TIC occurs, the satellite code, epoch value and
slew numbers are loaded, and a new phase programmed into
the Code DCO regardless of its previous value. Prior to the TIC
the channel operates with its previous settings.
Preset Mode has no effect on the Carrier DCO and
Carrier Cycle Counter.
If Preset mode is initiated, it should be allowed to operate
to completion. The required sequence of operations is as
follows:
(i) Write into CHx_SATCNTL to select the PRESET mode,
together with the appropriate new settings.
ii) Load the Code and Carrier DCO increment values.
Note: These will take effect immediately thereby influencing
the current measurements.
iii) Load the following Registers: CHx_CODE_DCO_PHASE,
CHx_CODE_SLEW and CHx_EPOCH_COUNT_LOAD. It is
important that the CHx_EPOCH_COUNT_LOAD occurs last,
because it enables the preset operation on the next TIC.
Interrupts
There are 2 interrupt sources: ACCUM_INT and
MEAS_INT. Their sense is dependant upon the selected
microprocessor interface mode. The default ACCUM_INT
period is 505.05µs. However, it can be reconfigured via the
PROG_ACCUM_INT register or by changing the
INTERRUPT_PERIOD or FRONT_END_MODE bits in the
SYSTEM_SETUP register. The default MEAS_INT period is
50ms. However, this can be reconfigured via the
PROG_TIC_HIGH and PROG_TIC_LOW registers.
Signal Path Delay
Introduced by Hardware Signal Processing
When it is desired to generate an accurate time reference
from GPS signals or to time–stamp position fixes the delays in
the receiver must be allowed for. The signal path delay has two
components, an Analogue path delay which varies with tem-
perature and component tolerances; and a Digital path delay
which is constant if oscillator drift variations are neglected.
The Digital delay is easier to estimate and is made up of
the following:
In Real_Input mode:
(i) The time from the sampling edge of the SIGN and MAG
bits in the front end (SAMPCLK) to the re–sampling in the
Sample Latch (175 ns less the propagation delay of
SAMPCLK to the Front–end).
GP2021
(ii) Plus the time for the correlation in the Correlator on these
same SIGN and MAG bits (125 ns).
(iii) Plus the delay in the accumulator to latch the sampled
data (175 ns ).
(iv) Less the time between the correlation and the TIC clock
phase which is before the accumulator latch phase (75 ns),
Giving a total of 400 ns less the SAMPCLK delay.
In Complex_Input mode:
(i) The time for the correlation in the Correlator on the SIGN
and MAG bits after sampling (114 ns).
(ii) Plus the delay in the accumulator to latch the sampled
data (171 ns ).
(iii) Less the time between the correlation and the TIC clock
phase which is before the accumulator latch phase (86 ns),
giving a total of 199 ns.
The Analog delay through the radio receiver is set by such
parameters as group delay in filters, which for the bandwidths
used for C/A code will be in the region of 1 to 2 ms and so
swamps the digital delay, but this can be measured and
corrected for.
Integrated Carrier Phase Measurement
The Correlator tracking channel hardware allows meas-
urement of integrated carrier phase through the
CHx_CARRIER_CYCLE_HIGH and _LOW and the
CHx_CARRIER_DCO_PHASE registers, which are part of
the Measurement Data sampled at every TIC. The
CHx_CARRIER_CYCLE_HIGH and _LOW registers contain
the (20 bit) number of positive–going zero crossings of the
Carrier DCO; this will be one more than the number of full
cycles elapsed ( 4 bits are in _HIGH and 16 in _LOW register).
The CHx_CARRIER_DCO_PHASE register contains the cy-
cle fraction or phase, with 10 bit resolution to give 2 π / 1024
radian increments.
To get the Integrated Carrier Phase over several TIC
periods all that is needed is to read the
CHx_CARRIER_CYCLE_HIGH and _LOW registers at every
TIC and sum the readings. This gives a number 1 higher than
the number of complete carrier cycles, when a carrier cycle is
measured from one positive–going zero crossing to the next.
To this number, the fractional carrier cycle at the end has
to be added, and the fractional carrier cycle at the beginning
has to be subtracted. Both numbers are read from the
CHx_CARR_DCO_PHASE register. The total phase change
can be calculated as follows :
Integrated Carrier Phase =
2 π * ∑ Numbers in Carrier Cycle Counter
+ final Carrier DCO phase
–Initial Carrier DCO phase
Fig. 22 shows how this equation is derived.
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