GP2021 Datasheet, PDF (43/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
ELECTRICAL CHARACTERISTICS(cont.)
T amb = –40°C to 85 °C, V DD = 5V 10%. The input thresholds and output voltage limits for the logic signal pins are
tested and guaranteed by production test. All other parameters are guaranteed by characterisation and design. They apply
within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristics
Symbol
Value
Min
Typ Max Units
Conditions
Power level 6 Outputs: types OP6
and OPT6
Output Voltage High
Output Voltage Low
Output short
circuit current
Tri–state output leakage current
Output capacitance
Power Level 3 Outputs : types OP3
and OPT3
Output Voltage High
Output voltage Low
Output short
circuit current
Tri–state output leakage current
Output capacitance
Power Level 2 Outputs: types OP2
and OPT2
Output voltage High
Output voltage Low
Output short
circuit current
Tri–state output leakage current
Output capacitance
Power Level 1 Outputs: types OP1
and OPT1
Output Voltage High
Output Voltage Low
Output short
circuit current
Tri–state output leakage current
Output capacitance
V _OH
V OL
IOS
IOZ
COUT
0.8V _DD
270
150
<10
5
V _OH
V _OL
IOS
IOZ
COUT
0.8V _DD
135
75
<10
5
V _OH
V
OL
IOS
IOZ
COUT
0.8V _DD
90
50
<10
5
V _OH
V _OL
IOS
IOZ
COUT
0.8V DD
45
25
<10
5
V
0.4
V
mA
mA
µA
pF
V
0.4
V
mA
mA
µA
pF
V
0.4
V
mA
mA
µA
pF
V
0.4
V
mA
mA
µA
pF
I _OH = –12mA
I _OL = 12mA
V _DD = max VO = V DD
V _DD = max VO = 0V
VOH = GND or V DD
I _OH = –6mA
I _OL = 6mA
V = max VO = V
DD
DD
V _DD = max VO = 0V
VOH = GND or V _DD
I _OH = –4mA
I = 4mA
OL
V_DD = max VO = V_DD
V_DD = max VO =0V
VOH = GND or V _DD
I _OH = –2mA
I _OL = 2mA
V_DD = max VO = V_DD
V_DD = mx VO = V_DD
VOH = GND or V
DD
Note 1: Any unused inputs must be tied High or Low.
Note 2: The input pair CLK_T, CLK_I may be driven by CMOS logic levels (D.C. coupled) or A.C. coupled or by a low amplitude differential
sinewave (D.C. coupled e.g. GP2010). If a single logic level is to be used this should drive CLK_T with the CLK_I pin biased to mid supply.
If a single sinewave clock is to be used this should drive CLK_T through a capacitor, with both of the CLK_T/CLK_I pins biased to
approximately two thirds supply. See Fig. 24 for a suggested circuit.
Note 3: These values apply when the 32kHz oscillator circuit is not running.
Note 4: The operation of the feature whereby input levels and output drive strengths can be modified is not guaranteed by the existing factory
testing procedure.
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