GP2021 Datasheet, PDF (30/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
sub-cycle phase measurement information and so
complements the information given by
CHx_CARRIER_CYCLE_HIGH and _LOW.
The register value is latched on each TIC and is not
protected by any overwrite protection mechanism.
CHx_CODE_DCO_INCR_HIGH,
X_DCO_INCR_HIGH,
MULTI_CODE_DCO_INCR_HIGH,
ALL_CODE_DCO_INCR_HIGH,
CHx_CODE_DCO_INCR_LOW,
MULTI_CODE_DCO_INCR_LOW,
ALL_CODE_DCO_INCR_LOW
(Write Address)
_INCR_HIGH bits 15 to 9: Not used in this operation.
_INCR_HIGH bits 8 to 0: More significant bits (24 to 16) of the
Code DCO phase increment when used before a
CODE_DCO_INCR_LOW.
_INCR_LOW bits 15 to 0: Less significant bits (15 to 0) of
the Code DCO phase increment.
The contents of registers _INCR_HIGH and _INCR_LOW
are combined to form the 25 bits of the
CHx_CODE_DCO_INCR register, the Code DCO phase
increment number. In order to write successfully, the top 9 bits
must be written first, to any of the _HIGH addresses. They will
be stored in a buffer and only be transferred into the increment
register of the DCO together with the _LOW word. A 25 bit
increment number is adequate for a 26 bit accumulator DCO
as the increment to the MSB is always zero.
The LSB of the INCR register represents a step given by:
Min Step Frequency
(in Real_Input mode)
= (40MHz/7)/2 26
= 85.14949mHz
Min Step Frequency
= (35MHz/6)/2 26
(in Complex_Input mode) = 86.92344mHz
The output Frequency
= CHx_CODE_DCO_INCR
* Min Step Frequency.
Note: The Code DCO drives the Code Generator to give half
chip time steps and so must be programmed to twice the
required chip rate. This means that the chip rate resolution is
42·57475mHz in Real_Input mode or 43.46172mHz in
Complex_mode.
The nominal frequency is 1.023000000 MHz before allowing
for Doppler shift or crystal error. Writing 016EA4A8H into the
CHx_CODE_DCO_INCR register will generate a chip rate of
1.022999968 MHz in Real_Input mode. In Complex_mode,
01672922H will generate a chip rate of 1.022999970 MHz.
CHx_CODE_DCO_PHASE
(Read Address)
Bits 15 to 10: Not used, (Low when read).
Bits 9 to 0: CHx_CODE_DCO_PHASE: Contains the ten more
significant bits (25 to 16) of the Code DCO phase accumulator
sampled at a TIC event. It is an unsigned integer valid from 0
to 1023. The weight of the least significant bit is 2 π /1024
radians, 2 π being half of a code chip, so the pseudorange
resolution is 1/2048 of a chip, (equivalent to 0·15 metre or
0·5ns).
30
The CHx_CODE_DCO_PHASE content is not protected by
any overwrite protection mechanism.
CHx_CODE_DCO_PRESET_PHASE,
MULTI_CODE_DCO_PRESET_PHASE,
ALL_CODE_DCO_PRESET_PHASE
(Write Address)
Bits 15 to 8: Not used.
Bits 7 to 0: More significant bits (25 to 18) of the Code DCO
phase which is to be loaded at the next TIC event in PRESET
mode.
In PRESET mode, the 8 bits of the
CHx_CODE_DCO_PRESET_PHASE register, with zeros
filling the lower bits, are transferred to the CODE DCO
accumulator on the next TIC. The previous accumulator
phase is totally overwritten. The PRESET_PHASE register is
a write–only register and it can be written to at any time in
PRESET mode or in UPDATE mode, but only has effect when
PRESET mode is entered. The weight of the least significant
bit of PRESET phase is 2 / 256 radians of a half chip cycle.
In UPDATE mode this register has no use other than as
preparation for PRESET mode.
Refer to Detailed Operation of GP2021 for further
information on PRESET mode. *
* Refer to page 9.
CHx_CODE_PHASE
(Read Address)
CHx_CODE_PHASE_COUNTER,
MULTI_CODE_PHASE_COUNTER,
ALL_CODE_PHASE_COUNTER
(Write Address)
Bits 15 to 11: Not used, Low when read.
Bits 10 to 0: CHx_CODE_PHASE (Read) – This is the state of
the Code Phase Counter, (an 11–bit binary up counter clocked
by the Code Generator Clock), stored on TIC. The phase is
expressed as a number of half code chips and ranges from 0
to 2046 half chips. A reading of 2046 is very rare and can only
occur if the TIC captures the Code phase just after the counter
reaches 2046 and before it is reset by a DUMP from the C/A
Code Generator. DUMP also increments the Epoch counter,
so the meaning of a phase value of 2046 + the previous Epoch
value is the same as a phase value of 0 + the incremented
Epoch value, and either is valid. If a TIC occurs during a Code
Slew the reading will be 0, and that channel’s Measurement
Data is of no use.
Bits 10 to 0: (Write) loads the 11 bits of the
CHx_CODE_PHASE_COUNTER. A write to these registers
is only possible in test mode, enabled by setting the TM_TEST
(bit of TEST_CONTROL) to High.
CHx_CODE_SLEW
(Read Address)
CHx_CODE_SLEW_COUNTER,
MULTI_CODE_SLEW_COUNTER,
ALL_CODE_SLEW_COUNTER
(Write Address)
Bits 15 to 11: Not used.
Bits 10 to 0 : An unsigned integer ranging from 0 to 2047
representing the number of code half chips to be slewed
immediately after the next DUMP if in UPDATE mode or after
the next TIC, if in PRESET mode. Since there are only 2046