GP2021 Datasheet, PDF (28/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
ACCUM_STATUS_A
(Read Address)
Bit
Bit Name
15
ACCUM_INT
14
Not used –LOW
13
Not used –LOW
12
Not used –LOW
11
CH11_NEW_ACCUM_DATA
10
CH10_NEW_ACCUM_DATA
9
CH9_NEW_ACCUM_DATA
8
CH8_NEW_ACCUM_DATA
7
CH7_NEW_ACCUM_DATA
6
CH6_NEW_ACCUM_DATA
5
CH5_NEW_ACCUM_DATA
4
CH4_NEW_ACCUM_DATA
3
CH3_NEW_ACCUM_DATA
2
CH2_NEW_ACCUM_DATA
1
CH1_NEW_ACCUM_DATA
0
CH0_NEW_ACCUM_DATA
ACCUM_STATUS_A is a register containing the state of
twelve status bits sampled and latched on the active edge of
every ACCUM_INT. They can also be sampled and latched on
request, by performing a write operation to STATUS. (This is
safe only if the interrupts are stopped, by setting
INTERRUPT_ENABLE bit to LOW in the SYSTEM_SETUP
register.) The microprocessor must respond to each
ACCUM_INT and read the channel registers before the next
DUMP is due in that channel.
The ACCUM_INT bit is set HIGH at every ACCUM_INT
and is reset by reading the ACCUM_STATUS_A register. This
status bit is reset by a hardware master reset but not by a
software reset (MRB).
The CHx_NEW_ACCUM_DATA status bit indicates that a
DUMP has occurred in that channel, and that new Accumulated
Data is available to be read.
Each bit is cleared by the trailing edge of a read of the
associated CHx_Q_PROMPT register or by a write to
CHx_ACCUM_RESET.
Note that the channel specific bits of this register will not
show their new value until after an active edge of ACCUM_INT
or a write to the STATUS register. Disabling a channel will
however, clear the bit immediately.
ACCUM_STATUS_B
(Read Address)
Bit
Bit Name
15
DISCIP_GLITCH
14
DISCIP
13
TIC
12
MEAS_INT
11
CH11_MISSED_ACCUM
10
CH10_MISSED_ACCUM
9
CH9_MISSED_ACCUM
8
CH8_MISSED_ACCUM
7
CH7_MISSED_ACCUM
6
CH6_MISSED_ACCUM
5
CH5_MISSED_ACCUM
4
CH4_MISSED_ACCUM
3
CH3_MISSED_ACCUM
2
CH2_MISSED_ACCUM
1
CH1_MISSED_ACCUM
0
CH0_MISSED_ACCUM
The lower 12 bits of ACCUM_STATUS_B bits are sampled
and latched on the active edge of every ACCUM_INT signal.
They can be sampled and latched on request by performing a
write operation to STATUS (as with ACCUM_STATUS_A).
The DISCIP_GLITCH bit will be set High if a glitch to Low
has occurred on the DISCIP pin since the last read of this
register. It is cleared by reading this ACCUM_STATUS_B
register. This bit is reset by a hardware master reset (RESETB
at Low) but not by a software reset. The minimum reliably
detectable glitch width is 25ns.
The DISCIP bit indicates the level on the DISCIP input pin
at the time this read occurs and may be used to interface a
hardware condition (such as a ready flag from a UART or the
PLL LOCK signal from a front–end) to the microprocessor
without using an interrupt. This bit is not reset by a hardware
master reset nor by an MRB.
The TIC bit is set High at every TIC and is cleared by
reading this ACCUM_STATUS_B register. Its purpose is to tell
the microprocessor that new Measurement Data is available. It
is reset by a hardware master reset (RESETB at Low) but not by
an MRB in RESET_CONTROL.
Provided that interrupts are enabled, the MEAS_INT bit is
set High at each TIC and 50 ms before each TIC ( if the TIC
period is greater then 50 ms), and is cleared by reading this
register. This bit can be used as a flag to the microprocessor, to
time software module swapping. It is reset by a hardware master
reset (RESETB at Low), but not by a software reset.
CHx_MISSED_ACCUM status bit indicates (when High) that
there has been missed Accumulated Data due to a new DUMP
in CHx before the previous data has been read. This bit is
latched until the associated CHx_ACCUM_RESET is written to.
If any data is missed due to the reading process being too slow
this must be allowed for in the software, such as by checking the
Navigation Message data bit transitions independently of the
sets of Accumulated Data reads. If too much data is lost the
system signal to noise ratio will be degraded. The primary
purpose of these bits is as a check on how well the tracking
routines are working – once the whole design is complete these
bits should not become set.
Note that the channel specific bits of this register will not
show their new value until after an active edge of ACCUM_INT
or a write to the STATUS register. Disabling a channel will
however, clear the bit immediately.
ACCUM_STATUS_C
(Read Address)
Bit
Bit Name
15
not used – LOW
14
not used – LOW
13
not used – LOW
12
not used – LOW
11
CH11_EARLY_LATEB
10
CH10_EARLY_LATEB
9
CH9_EARLY_LATEB
8
CH8_EARLY_LATEB
7
CH7_EARLY_LATEB
6
CH6_EARLY_LATEB
5
CH5_EARLY_LATEB
4
CH4_EARLY_LATEB
3
CH3_EARLY_LATEB
2
CH2_EARLY_LATEB
1
CH1_EARLY_LATEB
0
CH0_EARLY_LATEB
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