GP2021 Datasheet, PDF (24/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
PH₀
TIC ₀
K₁ Cycles
Y1
1 ^PKH
TIC ₁
2 ^Cycles
Y2
2^PH
TIC ₂
1. reading at TIC₀ :
CHx_CARR_DCO_PHASE₀ = PH₀
2. reading at TIC₁ :
CHx_CARR_DCO_PHASE₁ = PH₁
CHx_CARR_CYCLE₁ = K₁ + 1
3. reading at TIC₂ :
CHx_CARR_DCO_PHASE₂ = PH₂
CHx_CARR_CYCLE₂ = K₂ + 1
∆Y1 = 2π * K₁ + (2π – PH₀) + PH₁
= 2π(K₁ + 1) – PH₀ + PH₁
= 2π * (CHx_CARR_CYCLE₁ – CHx_CARR_DCO_PHASE₀ /1024 + CHx_CARR_DCO_PHASE₁/1024)
last
∑ • ∆Y = 2 π * ( CHx_CARR_CYCLE_i
i1
CHx_CARR_DCO_PHASE₀ 1024
CHx_CARR_DCO_PHASE_last 1024)
Note: The Carrier Cycle Counter value is stored at every TIC and the Counter is reset
Fig.22 Integrated carrier phase
This Integrated Carrier Phase may be related to the
delta–range, (the change in distance to each satellite). When
used with the orbital parameters of the satellites, the delta–
ranges give a measure of the receiver’s movement between
fixes, which is independent of those fixes and so can be used
to smooth them. It can also give a velocity directly. The delta–
ranges will be noisy and most of the value is due to satellite
movement so the determination of velocity must use data from
adequately separated TICs. For position smoothing all delta–
ranges may be included in the input to the navigation filter, as
that filter will perform a running average of the delta–ranges as
well as the ranges.
Timemark Generation
The GP2021 is capable of generating an accurate
TIMEMARK timing output on one of the discrete outputs if
required. TIMEMARK is intended to be a UTC aligned timing
output with an accurate 1 second period and a pulse width of
1ms. The TIMEMARK output is always derived from a rising
edge on TIC, and for UTC aligned operation the TIC counter
must be brought into phase with UTC. This is done by
modifying the division ratio of the TIC counter for a single TIC
period, by increasing or reducing the division ratio, thus
slewing the phase of TIC. Since the TIC counter is
incremented every 175ns which is not an exact sub–multiple
of 1 second it is also necessary to continually monitor the
relationship between TIC and UTC to keep TIC in phase with
UTC. Once TIC is in phase with UTC, the TIMEMARK output
can be derived from TIC using one of 2 methods both of which
involves writing to TIMEMARK_CONTROL: (1) The GP2021
can be armed to produce a TIMEMARK output at the next TIC
only, or (2) It can be programmed to give a TIMEMARK output
every n TICs starting at the next TIC.
A separate counter resets the TIMEMARK output giving
a 1ms pulse width. The TIC counter can be programmed with
an accuracy of 175ns in Real_Input mode or 171.4ns in
Complex_Input mode. This determines the accuracy of the
TIMEMARK output. If the TIC is continually synchronised to
keep the rising edge as close as possible to UTC, the internal
TIMEMARK will be within 100ns (4/7 x 175ns) of UTC in
Real_Input mode or 85.7ns (3/6 x 171.4ns) of UTC in
Complex_Input mode. In addition, there may be a delay of up
to 50ns in getting the TIMEMARK output off chip, giving a
maximum error of 150ns (Real_Input) or 135.7ns
(Complex_Input) between TIMEMARK and UTC. It should be
noted that due to the need to re–synchronise TIC, a jitter of up
to 175ns may be present on TIMEMARK, along with any jitter
and drift present on the input clock. The pulse width of
TIMEMARK (in seconds) is either (5714 + 2/7) * (7/ Master
Clock Frequency) for Real_Input mode giving 1.0000000ms
(assuming an accurate 40MHz master clock input) or (5833 +
1/6) * (6 / Master Clock Frequency) for Complex_Input mode
giving 0.9999714ms (assuming an accurate 35MHz master
clock input).
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