GP2021 Datasheet, PDF (6/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
Pin No
Signal Name
Type
31 ABORT/ MICRO_CLK O
32
DISCIO
I/O
33
A22 / READ
I
36
A21 / NCS
I
37
A20 / WREN
I
38 – 45
A<9:2>
I
46
A1 / ALE_IP
I
47
A0 / NRESET_IP
I
48– 54,
D<0:15>
I/O
57–65
66
PLL_LOCK
I
68
DISCOP
O
70
CLK_T
I
71
CLK_I
I
73
SAMPCLK
O
75
NBRAM / DISCIP4
I
76
SIGN0
I
77
MAG0
I
78
SIGN1
I
79
MAG1
I
80
DISCIP1
I
Description ARM System Mode
Description Standard Interface
Mode
Abort output to the microprocessor.
Generates a valid ARM Data Abort
sequence, triggered by a rising edge
at MULTI_FN_IO if this function is
enabled.
20MHz Clock output. Provides a
20MHz clock with a 1:1
mark-to-space ratio
Multi–purpose discrete input / output. After a GP2021 reset it is
configured as an input.
Address input from the microprocessor.
A<22:20> are decoded to select the
address space partitioning.
Read input from the
microprocessor. In Intel mode
it is the active Low read strobe.
In Motorola mode it is the Read
(High)/Write (Low) select line.
Address input from the microprocessor.
A<22:20> are decoded to select the
address space partitioning.
GP2021 Chip Select input
(Active Low).
Address input from the microprocessor
A<22:20> are decoded to select the
address space partitioning.
Write–Read Strobe input from
the microprocessor. In Intel
mode it is the active Low write
strobe. In Motorola mode it is
the active High Write-Read
strobe.
Address Inputs <9:2> from the microprocessor. These allow register
selection.
Address input 1 from the
microprocessor. A<1:0> are decoded
to provide individual byte write
selection via NW<3:0>.
Address Latch Enable input
from microprocessor (Active
High)
Address input 0 from the
microprocessor. A<1:0> are decoded
to provide individual byte write
selection via NW<3:0>.
Reset input (Active Low).
Bidirectional data bus.
PLL Lock Indicator input from RF section. When High this signa
indicates that the PLL within the RF section is in lock and the master
clock inputs have stabilised.
Multi–purpose discrete output.
Master clock input (40MHz).
Inverted Master clock input.
Sample Clock output to the front end. Provides a 5.714MHz clock with a
4:3 mark–to–space ratio.
Battery Backed RAM select input.
Defines the state of the NRAM output in
Power Down mode.
Multi–purpose discrete input.
SIGN0 input from the RF section.
MAG0 input from the RF section.
SIGN1 input from a second, optional, RF section.
MAG1 input from a second, optional, RF section.
Multi–purpose discrete input.
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