GP2021 Datasheet, PDF (4/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
TYPICAL GPS RECEIVER
Fig. 2 shows a typical GPS receiver employing a GP2010
RF front–end, a GP2021 correlator and an ARM60 32 bit RISC
microprocessor.
A single front end may be used, since all GPS satellites use
the same L1 frequency of 1575.42 MHz. However, in order to
achieve better sky coverage, it is sometimes desirable to use
more than one antenna. In this case, separate front ends will
be needed.
The RF section, GP2010, performs down conversion of
the L1 signal for digital baseband processing. The resultant
signal is then correlated in the GP2021 with an internally
generated replica of the satellite code to be received.
Individual codes for each channel may be selected
independently to enable acquisition and tracking of up to 12
different satellites simultaneously
The results of the correlations form the accumulated data
and are transferred to the microprocessor to give the
broadcast satellite data (the ’Navigation Message’) and to
control the software signal tracking loops.
The GP2021 can be interfaced to one of two styles of front
end. In Real_Input mode, the front end supplies either a 1
(sign) or 2 (sign and magnitude) bit signal to either the
SIGN0/MAG0 or SIGN1/MAG1 inputs of the GP2021.
Alteratively, in Real_Input mode, 2 separate front ends can be
connected to a single GP2021 and selected under software
control. The GP2015 and GP2010 are Real_Input mode front
ends.
In Complex_Input mode, the front end is required to supply
In–phase (I) and Quadrature (Q) signals to the SIGN0/MAG0
and SIGN1/MAG1 inputs respectively. Hence, only a single
front end can be used with each GP2021 in Complex_Input
mode.
L1 ANTENNA
GP2021
MEMORY
CONTROL
MEMORY
SIGN
MAG
SAMPCLK
GP2010 ^CLK_T
CLK_I
PLL_LOCK
WREN
READ
12
MICRO_CLK
CHANNEL
CORRELATOR
PERIPHERAL
FUNCTIONS
CONTROL
DATA
ADDR
ARM60
10MHz
TCXO
ACCUM_INT,MEAS_INT
TX/RX
SERIAL COMMS PORT
Fig. 2 Block diagram of typical ARM based receiver
PIN DESCRIPTION
All V SS and V DD pins must be connected in order to ensure reliable operation. Any unused inputs must be tied High or Low.
The Table below describes the pin functions in Real_Input mode and assumes a master clock input frequency of 40MHz.
Those pins whose functions differ in Complex_Input mode are described at the end of the table.
Note that those pin names containing a ‘/’ have dual functionality between ARM System and Standard Interface modes. The
Pin mnemonic for ARM System mode always precedes the ‘/’.
Pin No
15, 35,
56, 69,
72
14, 34,
55, 67,
74
1
Signal Name
V SS
V DD
MULTI_FN_IO
Type Description ARM System Mode
-
Ground Pin
Description Standard Interface
Mode
+ Power supply to device.
I/O Multi–function input / output. Its function is configured by the IO_CONFIG register.
After a GP2021 reset it acts as the Digital System Test Enable input. It can also
be configured as a discrete output, or a discrete input if certain conditions are met.
Can be configured as the TRIGGER
input to the DEBUG block in ARM
System mode.
4