GP2021 Datasheet, PDF (38/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
PERIPHERAL FUNCTIONS REGISTERS
The addresses for the Peripheral Functions Registers
are shown in the GP2021 Register Map.
These registers may be either 8 or 16 bits wide. Registers
which are byte wide are accessed via the top 8 bits of the data
bus, D<15:8>. During a byte wide read D<7:0> are held Low.
Each of the registers for the Real Time Clock, Dual UART,
System and General Control functions are described below.
Real Time Clock and Watchdog
The registers in the Real Time Clock are all byte wide.
RTC_LS,
RTC_2ND,
RTC_MS ,
(Read Addresses)
The clock time is output in these three eight bit read only
registers. All three registers are latched when a read is
performed of the LS Byte Register, so this should be read first.
In Power Down Mode the clock continues to run but access to
these registers is not possible.
CLOCK RESET
(Write Address)
A write to this address resets the clock divider and
counter, regardless of the data word written.
WATCHDOG RESET
(Write Address)
A write to this address resets the watchdog timer,
regardless of the data word written.
DUART
All the registers within the DUART are byte wide.
CONFIG_A,
CONFIG_B
(Write Address)
These registers allow the UARTs to be configured for
receive baud rate, parity and loopback. The configuration bit
functions are shown in Table 15. The missing binary
combinations of bit settings should not be used as the results
would be indeterminate.
Note that all bits are set Low by a UART A/B or a System reset,
thus causing UART A/B to default to a receive baud rate of
300, no parity and no loopback.
38
Bit Setting
Bit 11 10 9
00 0
00 0
00 1
00 1
01 0
01 0
01 1
01 1
10 0
Bit 13 12
00
11
10
Bit 14
0
1
Bit 15
0
1
Function
8 Receiver Baud Rate
0 300
1 600
0 1200
1 2400
0 4800
1 9600
0 19.2k
1 38.4k
0 76.8k
Parity
No parity–bit not set or
checked for
Odd parity–parity added
so that the toatl number
of '1's in the word is even
Even parity–parity added
so that the total number
of '1's in the word is even
Loopback
No loopback–normal
operation
Loopback–the Tx output
drives the Rx input and
Tx pin is held HIGH
Test mode
Test mode bit in Ch A
only used for chip testing
only. This bit must be set
Low for Normal operation
Test mode
Table 15: Configuration of UARTs through CONFIG_A
and CONFIG_B registers.
STATUS_A,
STATUS_B
(Read Address)
Reading from these register addresses will give the
current value of the channels status bits. The Status bit
functions are as shown in Table 16.
Bit SET (High) by CLEARER (Low) by RESET to
8 RX Valid Data
No RX Data
Low
Available
9 RX FIFO Full
RX FIFO Not Full
Low
10
RX FIFO
Read of UART Status Low
Overflow
Register
11
TX
TX Register Empty Low
Transmitting
12 TX FIFO Full
TX FIFO Not Full
Low
13 Parity Error Read of UART Status Low
Occured
Register
Low
14 Framing Error Read of Uart Status Low
15
Not Used
(Held High)
Table 16: Status bits available when reading the
STATUS_A and STATUS_B registers.