GP2021 Datasheet, PDF (46/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
Notes : 1. Although MULTI_FN_IO is capable of being used as a Discrete input, this is not advised since if this pin is
driven High at power up, Digital Test Mode will be selected and correct operation will not ensue.
2. Output has power level 1 when OPS_DRIVE_SEL is Low in the SYSTEM_SETUP Register.
Output has power level 2 when OPS_DRIVE_SEL is High in the SYSTEM_SETUP Register.
3. Input has TTL thresholds in ARM System mode, but has Schmitt Trigger (type ST2) thresholds in Standard
Interface mode.
4. Output has power level 3 when OPS_DRIVE_SEL is Low in the SYSTEM_SETUP Register.
Output has power level 6 when OPS_DRIVE_SEL is High in the SYSTEM_SETUP Register.
5. Input has Schmitt Trigger type ST2 thresholds when IPS_3V_MODE is Low in the SYSTEM_SETUP
Register. When High they have ST1 thresholds.
6. Usually connected to NFIQ of the ARM60 Processor.
7. Usually connected to NIRQ of the ARM60 Processor.
8. Characterisation data for this pin is with C L = 10pF.
9. Characterisation data for this pin is with C L = 20pF.
10. Characterisation data for this pin is with C L = 30pF
11. Characterisation data for this pin is with C L = 50pF.
12. Characterisation data for this pin is with C L = 55pF.
13. Setup and Hold times for the GPS data applied on pins SIGN0, MAG0, SIGN1 and MAG1 are with respect to
the rising edge of SAMPCLK. Setup time = 15ns, Hold time = –1ns (i.e. data should not change during the
period between 15ns and1ns before the rising edge of SAMPCLK; where SAMPCLK is assumed to be un
loaded. The SAMPCLK signal will tend to be further delayed by about 0.1ns / pF of load capacitance).
V_DD
V_DD
100k
CLK_T
600mV
SINE
WAVE
100k
100k
CLK_T
CLK_I
0.1 TO 1nF
CLK_I
100k
OR
180k
0.1 TO 1nF
OR
V_SS
V_SS
SINGLE ENDED CMOS
SINGLE 600mV SINEWAVE
GP2010
DIFFERENTIAL
OUTPUT
OPCLK+
OPCLK–
CLK_T
CLK_I
DIFFERENTIAL
Fig 24 : Clock interconnect options
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