GP2021 Datasheet, PDF (14/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
PLL_LOCK
NRESET_OP
MICRO_CLK
MCLK
4 CYCLES
50ms
Fig. 11 : PLL_LOCK Hardware Reset Generation
NRESET_IP
NRESET_OP
4 CYCLES
MICRO_CLK
Fig. 12 : NRESET_IP Hardware Reset Generation
Discrete I/O
The GP2021 contains a number of pins which may be used
as discrete inputs or discrete outputs for general purpose
system monitoring and control applications. The actual pins
which may be used for each function vary according to the
application and the interface mode of the GP2021.Table 5
shows a list of possible discrete inputs and outputs and the
modes in which they may be used. The level on all discrete
inputs can be read from the IO_CONFIG register. The status
of the DISCIP pin may also be read from
ACCUM_STATUS_B. The discrete outputs are controlled via
either the SYSTEM_SETUP or IO_CONFIG registers.
Discrete Inputs
Pin Name
NRW/DISCIP3
NOPC/NINTELMOT
NMREQ/DISCIP2
NBW/WRPROG
DISCIO
NBRAM/DISCIP4
MULTI_FN_IO
SIGN0, MAG0
SIGN1, MAG1
DISCIP1
RXA
RXB
Discrete Outputs
Pin Name
DISCOP
DISCIO
MULTI_FN_IO
Read Location
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
IO_CONFIG
ACCUM_STATUS_B
IO_CONFIG
IO_CONFIG
Conditions for use as Discrete Input
Standard Interface mode.
ARM System mode (debug disabled).
Standard Interface mode.
Motorola mode only.
DISCIO configured as discrete Input.
Standard Interface Mode.
MULTI_FN_IO configured as discrete input.
Single real input mode (GP2010 or GP2015) front end using
SIGN0, MAG0.
Single real input mode (GP2010 or GP2015) front end using
SIGN1, MAG1.
Always available – dedicated Discrete Input.
UART Channel A not used.
UART Channel B not used.
Configuration
Possible Outputs
Location
SYSTEM_SET_UP
High, Low, CH0 Dump, TIMEMARK, 100kHz Square Wave, Scan Out.
IO_CONFIG
High, Low, TIMEMARK, 100kHz Square Wave.
IO_CONFIG
High, Low, TIMEMARK, 100kHz Square Wave.
Table 5 : Discrete Input/Output Configuration
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