GP2021 Datasheet, PDF (33/62 Pages) Mitel Networks Corporation – GPS 12 channel Correlator Advance Information

GP2021
14 13 CODE SELECT
0
0
Early code
0
1
Late code
1
0
Dithering code
(alternating early and late)
1
1
Early–minus–late code
Table 10: TRACK_SEL bit settings for Tracking arm
code selection.
When the dithering code has been selected, the Tracking
arm will use the EARLY code for 20 periods of the Gold code,
the LATE code for the next 20 periods and then this process
of alternating between Early and Late code will be repeated
indefinitely. The Tracking Arm will toggle between Early or
Late Codes on every increment of a 20ms Epoch Count. Its
state can be determined by reading the ACCUM_STATUS_C
register.
The output code is a sequence of +1’s and –1’s for all code
types except EARLY–MINUS–LATE where the result can also
be a 0. In EARLY–MINUS–LATE mode the values are not the
+2,0, –2 that results from the calculation (+1 or –1) – (+1 or
–1), but are halved to +1, 0, –1. This must be considered when
choosing thresholds in the software as the correlation results
will be exactly half of the values otherwise expected.
GPS NGLON, bit 15: Setting this bit to Low changes the C/A
code generator mode to GLONASS mode, to generate the
fixed 511 bit sequence used by all GLONASS Satellites. After
a master reset, GPS mode is selected, but with all zeros in the
G2 generator, the G1 code is seen at the output of the C/A
code generator.
MEAS_STATUS_A
(Read Address)
Bit
15 to 14
Bit Name
Not Used
13
TIC
12
MEAS_INT
11
CH11_MISSED_MEAS_DATA
10
CH10_MISSED_MEAS_DATA
9
CH9_MISSED_MEAS_DATA
8
CH8_MISSED_MEAS_DATA
7
CH7_MISSED_MEAS_DATA
6
CH6_MISSED_MEAS_DATA
5
CH5_MISSED_MEAS_DATA
4
CH4_MISSED_MEAS_DATA
3
CH3_MISSED_MEAS_DATA
2
CH2_MISSED_MEAS_DATA
1
CH1_MISSED_MEAS_DATA
0
CH0_MISSED_MEAS_DATA
When a CHx_MISSED_MEAS_DATA status bit is High,
it indicates that one or more sets of measurement data have
been missed since the last read from this register. It is set High
by a read from the Code Phase Counter of the same channel,
when the previous value in the Code Phase Counter has not
been read, and is reset by a read from the MEAS_STATUS_A
register or by disabling the channel.
If this register is always read after the Code Phase
Counter, it indicates whether measurement data has been
missed before the last read of the Code Phase Counter. All
CHx_MISSED_MEAS_DATA bits are set Low by a hardware
or software reset.
The MEAS_INT bit is set High at each TIC and 50 ms
before each TIC ( if TIC period is greater then 50 ms), and is
cleared by reading this register. The purpose of the bit, is a flag
to the microprocessor, to time software module swapping.
This bit is reset by a hardware master reset (RESETB at Low)
but not by a software reset.
The TIC bit is set High at every TIC and is cleared by
reading this register. The purpose of the bit is to tell the
microprocessor that new Measurement Data is available. This
bit is reset by a hardware master reset (RESETB at Low) but
not by an MRB in RESET_CONTROL.
MULTI_CHANNEL_SELECT
(Write Address)
Bit
15 to 12
Bit Name
Not Used
11
CH11_SELECT
10
CH10_SELECT
9
CH9_SELECT
8
CH8_SELECT
7
CH7_SELECT
6
CH6_SELECT
5
CH5_SELECT
4
CH4_SELECT
3
CH3_SELECT
2
CH2_SELECT
1
CH1_SELECT
0
CH0_SELECT
CHx_SELECT, when set High, enables the Multi–
channel write operations on CHx. This may be used to set
several channels to mostly the same conditions. For a parallel
search for one satellite, operations such as setting each
Carrier DCO to the same frequency; or during that search, to
adjust all selected channels by the same value, (such as a
Code Slew to shift the code phases together to a new search
area) could use this feature.
All CHx_SELECT are set Low by a (hardware or
software) master reset.
PROG_ACCUM_INT
(Write Address)
Bits 15 to 13: Not Used.
Bits 12 to 0: ACCUM_INT Division Ratio.
The PROG_ACCUM_INT register location operates in
conjunction with the INTERRUPT_PERIOD bit of the
SYSTEM_SETUP register to set the period of the
ACCUM_INT output. ACCUM_INT is generated by a 13 bit
binary down counter which counts down to zero, producing an
ACCUM_INT output. It then loads to a preset value stored in
its preset register and starts to count down again. If the preset
value is P, the count sequence is P, P–1, P–2, ..., 1, 0, P, P–
1. Hence, the counter divides by P+1, producing an output with
a period of (P+1) * clock period. Since the ACCUM_INT
counter is clocked by the multi–phase clock, the clock rate is
either 7 * clock period (nominally 40MHz, i.e. 25ns) for
Real_Input mode, or 6 * clock period (nominally 35MHz, i.e.
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