MT40A512M16JY-075EAIT Datasheet, PDF (96/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Gear-Down Mode
• Additive latency (MR1[4:3]): CL - 2
• CAS WRITE latency (MR2 A[5:3]): Even number of clocks
• CS to command/address latency mode (MR4[8:6]): Even number of clocks
• CA parity latency mode (MR5[2:0]): Even number of clocks
Figure 38: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization)
CK_c
CK_t
DRAM
internal CLK
t_DSRX
TdkN
TdkN + N_even
RESET_n
CKE
CS_n
Command
tXPR_GEAR
tSYNC_GEAR
1N sync pulse
tCMD_GEAR
N^tCK_setup N^tCK_hold
MRS
Configure DRAM
to 1/4 rate
N^tCK_setup N^tCK_hold
NOP
Figure 39: Clock Mode Change After Exiting Self Refresh
CK_c
CK_t
TdkN
DRAM
internal CLK
CKE
CS_n
Command
tXPR_GEAR
tSYNC_GEAR
1N sync pulse
tCMD_GEAR
N^tCK_setup
N^tCK_hold
MRS
Configure DRAM
to 1/4 rate
N^tCK_setup N^tCK_hold
NOP
2N mode
Valid
Time Break
Don’t Care
TdkN + N_even
2N mode
Valid
Time Break
Don’t Care
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
96
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