MT40A512M16JY-075EAIT Datasheet, PDF (322/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Current Specifications – Limits
Table 147: I_DD, I_PP, and I_DDQ Current Limits; Die Rev. B (–40° ≤ T_C ≤ +105°C) (Continued)
Symbol
I_PP6: Auto self refresh I_PP current²³
I_DD7: Bank interleave read current
I_PP7: Bank interleave read I_PP current
I_DD8: Maximum power-down current
Width
×8
×16
×8
×16
×8
×16
×8
×16
DDR4-2666
(-075E)
5
5
184
264
15
20
27
28
DDR4-2400
(-083E)
5
5
184
264
15
20
27
28
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (–40°C–+85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-
ture range of operation (–40°C–+105°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (–40°C–+45°C).
4. I_DD6RT and I_DD6AT values are typical.
5. When additive latency is enabled for I_DD0, current changes by approximately 0%.
6. When additive latency is enabled for I_DD1, current changes by approximately +5% (×4/
×8), +4% (×16).
7. When additive latency is enabled for I_DD2N, current changes by approximately +0%.
8. When DLL is disabled for I_DD2N, current changes by approximately –23%.
9. When CAL is enabled for I_DD2N, current changes by approximately –25%.
10. When gear-down is enabled for I_DD2N, current changes by approximately 0%.
11. When CA parity is enabled for I_DD2N, current changes by approximately +7%.
12. When additive latency is enabled for I_DD3N, current changes by approximately +0.6%.
13. When additive latency is enabled for I_DD4R, current changes by approximately +5%.
14. When read DBI is enabled for I_DD4R, current changes by approximately 0%.
15. When additive latency is enabled for I_DD4W, current changes by approximately +3%(×4/
×8), +4%(×16).
16. When write DBI is enabled for I_DD4W, current changes by approximately 0%.
17. When write CRC is enabled for I_DD4W, current changes by approximately +10%(×4/×8),
+10%(×16).
18. When CA parity is enabled for I_DD4W, current changes by approximately +12% (×8),
+12% (×16).
19. When 2X REF is enabled for I_DD5B, current changes by approximately –14%.
20. When 4X REF is enabled for I_DD5B, current changes by approximately –33%.
21. I_PP0 test and limit is applicable for I_DD0 and I_DD1 conditions.
22. I_PP3N test and limit is applicable for all I_DD2x, I_DD3x, I_DD4x, and I_DD8 conditions; that is, test-
ing I_PP3N should satisfy the I_PPs for the noted I_DD tests.
23. I_PP6x is applicable to I_DD6N, I_DD6E, I_DD6R, and I_DD6A conditions.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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