MT40A512M16JY-075EAIT Datasheet, PDF (186/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Rising data strobe edge parameters:
• ^tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela-
tive to CK.
• ^tDQSCK is the actual position of a rising strobe edge relative to CK.
• ^tQSH describes the data strobe high pulse width.
• ^tHZ(DQS) DQS strobe going to high, nondrive level (shown in the postamble section
of the figure below).
Falling data strobe edge parameters:
• ^tQSL describes the data strobe low pulse width.
• ^tLZ(DQS) DQS strobe going to low, initial drive level (shown in the preamble section
of the figure below).
Figure 119: Clock-to-Data Strobe Relationship
RL measured
to this point
CK_t
CK_c
t_{DQSCK (MIN)}
t_{DQSCK (MIN)}
t_{DQSCK (MIN)}
t_{DQSCK (MIN)}
DQS_t, DQS_c
Early Strobe
t_{LZ(DQS) MIN}
t_RPRE
DQS_t, DQS_c
Late Strobe
t_{LZ(DQS) MAX}
t_RPRE
t_QSH
Bit 0
t_QSL
Bit 1
t_QSH
Bit 2
t_QSL
Bit 3
t_{DQSCK (MAX)}
t_{DQSCK (MAX)}
t_QSH
Bit 4
t_QSL
Bit 5
t_{DQSCK (MAX)}
Bit 6
Bit 7
t_RPST
t_{DQSCK (MAX)}
Bit 0
t_QSH
Bit 1
t_QSL
Bit 2
t_QSH
Bit 3
t_QSL
Bit 4
Bit 5
Bit 6
t_{HZ(DQS) MIN}
t_RPST
Bit 7
t_{HZ(DQS) MAX}
Notes:
1. Within a burst, the rising strobe edge will vary within ^tDQSCKj while at the same volt-
age and temperature. However, when the device, voltage, and temperature variations
are incorporated, the rising strobe edge variance window can shift between ^tDQSCK
(MIN) and ^tDQSCK (MAX).
A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a devi-
ce's actual ^tDQSCK (MAX). A timing of this window's left inside edge (earliest) from ris-
ing CK_t, CK_c is limited by ^tDQSCK (MIN).
2. Notwithstanding Note 1, a rising strobe edge with ^tDQSCK (MAX) at T(n) can not be im-
mediately followed by a rising strobe edge with ^tDQSCK (MIN) at T(n + 1) because other
timing relationships (^tQSH, ^tQSL) exist: if ^tDQSCK(n + 1) < 0: ^tDQSCK(n) < 1.0 ^tCK - (^tQSH
(MIN) + ^tQSL (MIN)) - | ^tDQSCK(n + 1) |.
3. The DQS_t, DQS_c differential output HIGH time is defined by ^tQSH, and the DQS_t,
DQS_c differential output LOW time is defined by ^tQSL.
4. ^tLZ(DQS) MIN and ^tHZ(DQS) MIN are not tied to ^tDQSCK (MIN) (early strobe case), and
t_{LZ(DQS) MAX and} t_{HZ(DQS) MAX are not tied to} t_{DQSCK (MAX) (late strobe case).}
5. The minimum pulse width of READ preamble is defined by ^tRPRE (MIN).
6. The maximum READ postamble is bound by ^tDQSCK (MIN) plus ^tQSH (MIN) on the left
side and ^tHZDSQ (MAX) on the right side.
7. The minimum pulse width of READ postamble is defined by ^tRPST (MIN).
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
186
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