MT40A512M16JY-075EAIT Datasheet, PDF (187/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
8. The maximum READ preamble is bound by ^tLZDQS (MIN) on the left side and ^tDQSCK
(MAX) on the right side.
Read Timing – Data Strobe-to-Data Relationship
The data strobe-to-data relationship is shown below and is applied when the DLL is en-
abled and locked.
Note: ^tDQSQ: both rising/falling edges of DQS; no ^tAC defined.
Rising data strobe edge parameters:
• ^tDQSQ describes the latest valid transition of the associated DQ pins.
• ^tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
• ^tDQSQ describes the latest valid transition of the associated DQ pins.
• ^tQH describes the earliest invalid transition of the associated DQ pins.
Data valid window parameters:
• ^tDVWd is the Data Valid Window per device per UI and is derived from [ ^tQH - ^tDQSQ]
of each UI on a given DRAM
• ^tDVWp is the Data Valid Window per pin per UI and is derived [ ^tQH - ^tDQSQ] of each
UI on a pin of a given DRAM
Figure 120: Data Strobe-to-Data Relationship
CK_c
CK_t
Command³
T0
READ
Address⁴
Bank,
Col n
T1
T2
DES
DES
RL = AL + CL
DQS_t, DQS_c
DQ²
(Last data )
DQ²
(First data no longer)
All DQ collectively
T9
T10
T11
T12
T13
T14
T15
DES
DES
DES
DES
DES
DES
DES
t_{DQSQ (MAX)}
t_{RPRE (1nCK)}
t_{DQSQ (MAX)}
t_RPST
t_QH
t_QH
D_OUT
n
D_OUT
n
D_OUT
n
D_OUT
n+1
D_OUT
n+2
D_OUT
n+3
D_OUT
n+4
D_OUT
n+5
D_OUT
n+6
D_OUT
n+7
t_DVWp
D_OUT
n+1
D_OUT
n+2
D_OUT
n+3
D_OUT
n+4
D_OUT
n+5
D_OUT
n+6
D_OUT
n+7
t_DVWp
D_OUT
n+1
D_OUT
n+2
D_OUT
n+3
D_OUT
n+4
D_OUT
n+5
D_OUT
n+6
D_OUT
n+7
t_DVWd
t_DVWd
T16
DES
Don’t Care
Notes:
1. BL = 8, RL = 11 (AL = 0, CL = 1) , Premable = 1^tCK.
2. D_OUT n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0.
5. Output timings are referenced to V_DDQ, and DLL on for locking.
6. ^tDQSQ defines the skew between DQS to data and does not define DQS to clock.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
187
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