MT40A512M16JY-075EAIT Datasheet, PDF (92/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Figure 34: MPR Back-to-Back WRITE Timing
T0
CK_c
CK_t
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
Command WRITE
DES
Address Add¹
Valid
DES
DES
t_{WR_MPR}
Valid
Add¹
WRITE
Valid
DES
Valid
DES
Add
DES
Valid
DES
DES
Valid
Valid
DES
Valid
DES
DES
Valid
Valid
CKE
DQS_t,
DQS_c
DQ
Time Break
Note:
1. Address setting:
BA1 and BA0 indicate the MPR location
A[7:0] = data for MPR
A10 and other address pins are "Don’t Care"
MPR REFRESH Waveforms
The following waveforms show MPR accesses interaction with refreshes.
Don’t Care
Figure 35: REFRESH Timing
CK_c
CK_t
Command
Address
T0
Ta0
Ta1
MPR Enable
PREA
MRS¹
DES
t_RP
t_MOD
Valid
Valid
Valid
Tb0
REF²
Valid
Tb1
DES
Valid
Tb2
DES
Valid
Tb3
Tb4
DES
DES
t_RFC
Valid
Valid
Tc0
DES
Valid
Tc1
DES
Valid
Tc2
Valid
Valid
Tc3
Valid
Valid
Tc4
Valid
Valid
Time Break
Don’t Care
Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1). Redirect all subsequent read and
writes to MPR locations.
2. 1x refresh is only allowed when MPR mode is enabled.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
92
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