MT40A512M16JY-075EAIT Datasheet, PDF (90/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is
fixed at 0, 1, 2, 3, T, T, T, T)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
Figure 32: MPR READ-to-WRITE Timing
T0
T1
T2
Ta0
Ta1
CK_c
CK_t
Command READ
DES
DES
DES
DES
Address Add¹
Valid
Valid
Valid
Valid
Ta2
DES
Valid
Ta3
DES
Valid
Ta4
DES
Valid
Ta5
DES
Valid
Ta6
Tb0
Tb1
DES
WRITE
t_MPRR
Valid
Add²
DES
Valid
Tb2
DES
Valid
CKE
DQS_t,
DQS_c
DQ
MPR Writes
PL³ + AL + CL
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
Time Break
Don’t Care
Notes:
1. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01
2. Address setting:
BA1 and BA0 indicate the MPR location
A[7:0] = data for MPR
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0].
Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will
maintain the new written values unless re-initialized or there is power loss.
The following steps are required to use the MPR to write to mode register MPR Page 0.
1. The DLL must be locked if enabled.
2. Precharge all; wait until ^tRP is satisfied.
3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR
Page 0); writes to 01, 10, and 11 are not allowed.
4. ^tMRD and ^tMOD must be satisfied.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
90
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