MT40A512M16JY-075EAIT Datasheet, PDF (103/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Command/Address Parity
Table 36: Mode Register Setting for CA Parity
CA Parity Latency
MR5[2:0]¹
000 = Disabled
001 = 4 clocks
010 = 5 clocks
011 = 6 clocks
100 = 8 clocks
101 = Reserved
110 = Reserved
111 = Reserved
Applicable Speed Bin
N/A
1600, 1866, 2133
2400, 2666
2933, 3200
RFU
RFU
RFU
RFU
Parity Error Status Parity Persistent Mode
Erroneous CA
Frame
MR5 [4] 0 = Clear
MR5 [4] 1 = Error
C[2:0], ACT_n, BG1,
BG0, BA[1:0], PAR,
MR5 [9] 0 = DisabledMR5
[9] 1 = Enabled
A17, A16/RAS_n, A15/
CAS_n, A14/WE_n,
A[13:0]
Notes:
1. Parity latency is applied to all commands.
2. Parity latency can be changed only from a CA parity disabled state; for example, a direct
change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to
PL = 4.
3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL.
READ latency = AL + CL + PL.
Figure 46: Command/Address Parity During Normal Operation
CK_c
CK_t
Command/
Address
T0
Valid²
T1
Valid²
Ta0
Valid²
t_{PAR_UNKNOWN}2
Ta1
Ta2
Tb0
Tc0
Tc1
Td0
Te0
Error
Valid
Valid
t_{PAR_ALERT_ON}
Valid
DES²
t > 2nCK
t_{PAR_ALERT_PW}1
DES²
Valid³
t > 1nCK + 3ns
ALERT_n
Te1
Valid³
Valid²
DES² _{Command execution unknown}
Error
Valid _{Command not executed}
Valid³ Command executed
Don’t Care
Time Break
Notes:
1. DRAM is emptying queues. Precharge all and parity checking are off until parity error
status bit is cleared.
2. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE
CRC occurs during the ^tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located
at MR5[3] may or may not get set.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit is cleared.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
103
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