MT40A512M16JY-075EAIT Datasheet, PDF (325/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Speed Bin Tables
DDR4 DRAM timing is primarily covered by two types of tables: the speed bin tables in
this section and those tables found in the Electrical Characteristics and AC Timing Pa-
rameters section. The timing parameter tables define the applicable timing specifica-
tions based on the speed rating. The speed bin tables below list the ^tAA, ^tRCD, ^tRP, ^tRAS
and ^tRC limits of a given speed mark and are applicable to the CL settings in the lower
half of the table provided they are applied in the correct clock range, which is noted.
Table 149: DDR4-1600 Speed Bins and Operating Conditions
DDR4-1600 Speed Bin
CL-nRCD-nRP
Parameter
Internal READ command to first data
Internal READ command to first data
with read DBI enabled
ACTIVATE to internal READ or WRITE
delay time
PRECHARGE command period
ACTIVATE-to-PRECHARGE command
period
ACTIVATE-to-ACTIVATE or REFRESH
command period
READ: non-
DBI
READ: DBI WRITE
CL = 9
CL = 11
CWL = 9
CL = 10
CL = 12
CWL = 9
CL = 10
CL = 12
CWL = 9, 11
CL = 11
CL = 13
CWL = 9, 11
CL = 12
CL = 14
CWL = 9, 11
Supported CL settings
Supported CL settings with read DBI
Supported CWL settings
Symbol
t_AA
t_{AA_DBI}
t_RCD
t_RP
t_RAS
t_RC6
Symbol
t_CK4
t_CK4
t_CK4
t_CK4
t_CK4
-125F
10-10-10
Min
Max
12.50 19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
12.50
–
12.50
35
–
9 × ^tREFI
t_{RAS +}
–
t_RP
Min
Max
1.5
1.9
1.5
1.9
1.25
<1.5
1.25
<1.5
1.25
<1.5
9–12
11–14
9, 11
-125E
11-11-11
Min
Max
13.75⁵ 19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
13.75⁵
–
13.75⁵
–
35
9 × ^tREFI
t_{RAS +}
–
t_RP
Min
Max
1.5
1.9
1.5
1.9
Reserved
1.25
<1.5
1.25
<1.5
9, 10, 11, 12
11, 12, 13, 14
9, 11
-125
12-12-12
Min
Max
15.00 19.00
t_AA
(MIN) +
2nCK
t_AA
(MAX) +
2nCK
15.00
–
Unit
ns
ns
ns
15.00
–
ns
35
9 × ^tREFI ns
t_{RAS +}
–
ns
t_RP
Min
Max
Reserved
1.5
1.9
Reserved
Reserved
1.25
<1.5
10, 12
12, 14
9, 11
Unit
ns
ns
ns
ns
ns
nCK
nCK
nCK
Notes:
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. ^tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation at defined clock rates.
6. When calculating ^tRC and ^tRP in clocks, values may not be used in a combination that
would violate ^tRAS.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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