MT40A512M16JY-075EAIT Datasheet, PDF (237/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation with CA Parity Enabled
8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 189: Consecutive Write (BL8) with 1^tCK Preamble and CA Parity in Different Bank Group
T0
T1
T2
T3
T4
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
CK_c
CK_t
Command WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_WR
t_{CCD_S = 4}
4 Clocks
t_WTR
Bank Group
BGa
BGb
Address
Address
Bank
Col n
Bank
Col b
Parity Valid
DQS_t,
DQS_c
DQ
Valid
WL = PL + AL + CWL = 13
t_WPRE
t_WPST
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
WL = PL + AL + CWL = 13
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1^tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-
mands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
ble.
6. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
237
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.