MT40A512M16JY-075EAIT Datasheet, PDF (126/358 Pages) Micron Technology – 8Gb: x4, x8, x16 DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Hard Post Package Repair
Hard Post Package Repair
All banks must be precharged and idle. DBI and CRC modes must be disabled. Both
sPPR and hPPR must be disabled. sPPR is disabled with MR4[5] = 0. hPPR is disabled
with MR4[13] = 0, which is the normal state, and hPPR is enabled with MR4 [13]= 1,
which is the hPPR enabled state. There are two forms of hPPR mode. Both forms of
hPPR have the same entry requirement as defined in the sections below. The first com-
mand sequence uses a WRA command and supports data retention with a REFRESH
operation except for the bank containing the row that is being repaired; JEDEC has re-
laxed this requirement and allows BA[0] to be a don't care regarding the banks which
are not required to maintain data a REFRESH operation during hPPR. The second com-
mand sequence uses a WR command (a REFRESH operation can't be performed in this
command sequence). The second command sequence doesn't support data retention
for the target DRAM.
hPPR Row Repair - Entry
As stated above, all banks must be precharged and idle. DBI and CRC modes must be
disabled, and all timings must be followed as shown in the timing diagram that follows.
All other commands except those listed in the following sequences are illegal.
1. Issue MR4[13] 1 to enter hPPR mode enable.
a. All DQ are driven HIGH.
2. Issue four consecutive guard key commands (shown in the table below) to MR0
with each command separated by ^tMOD. The PPR guard key settings are the same
whether performing sPPR or hPPR mode.
a. Any interruption of the key sequence by other commands, such as ACT, WR,
RD, PRE, REF, ZQ, and NOP, are not allowed.
b. If the guard key bits are not entered in the required order or interrupted with
other MR commands, hPPR will not be enabled, and the programming cycle
will result in a NOP.
c. When the hPPR entry sequence is interrupted and followed by ACT and WR
commands, these commands will be conducted as normal DRAM com-
mands.
d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a sup-
plier perspective and the user should rely on vendor datasheet.
Table 41: PPR MR0 Guard Key Settings
MR0
BG1:0 BA1:0 A17:12 A11
A10
A9
A8
A7
A6:0
First guard key
0
0
xxxxxx
1
1
0
0
1
1111111
Second guard key
0
0
xxxxxx
0
1
1
1
1
1111111
Third Guard key
0
0
xxxxxx
1
0
1
1
1
1111111
Fourth guard key
0
0
xxxxxx
0
0
1
1
1
1111111
hPPR Row Repair – WRA Initiated (REF Commands Allowed)
1. Issue an ACT command with failing BG and BA with the row address to be re-
paired.
2. Issue a WRA command with BG and BA of failing row address.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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