PIC24HJ16GP304-E Datasheet, PDF (99/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
9.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 family of devices.
However, it is not intended to be a com-
prehensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 9. Watchdog Timer
and Power Savings Modes” (DS70196)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices provide the ability to manage power
consumption by selectively managing clocking to the
CPU and the peripherals. In general, a lower clock
frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power.
PIC24HJ32GP202/204 and PIC24HJ16GP304
devices can manage power consumption in four
different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of the above methods can be used to
selectively customize an application’s power
consumption while still maintaining critical application
features, such as timing-sensitive communications.
9.1 Clock Frequency and Clock
Switching
PIC24HJ32GP202/204 and PIC24HJ16GP304 devices
allow a wide range of clock frequencies to be selected
under application control. If the system clock
configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSC bits (OSCCON<10:8>). The
process of changing a system clock during operation,
as well as limitations to the process, are discussed in
more detail in Section 8.0 “Oscillator
Configuration”.
9.2 Instruction-Based Power-Saving
Modes
PIC24HJ32GP202/204 and PIC24HJ16GP304 devices
have two special power-saving modes that are entered
through the execution of a special PWRSAV instruction.
Sleep mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. Example 9-1 shows the Assembler syntax of
the PWRSAV instruction.
Note:
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1 SLEEP MODE
In the Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled
• The LPRC clock continues to run if the WDT is
enabled
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode
• Some device features or peripherals may continue
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into Sleep mode
; Put the device into Idle mode
© 2007-2011 Microchip Technology Inc.
DS70289H-page 99