PIC24HJ16GP304-E Datasheet, PDF (61/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
FIGURE 6-3:
VDD
SYSRST
BROWN-OUT SITUATIONS
TBOR + TPWRT
VBOR
VDD
SYSRST
VDD dips before PWRT expires
VDD
SYSRST
TBOR + TPWRT
TBOR + TPWRT
VBOR
VBOR
6.3 External Reset (EXTR)
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
to Section 22.0 “Electrical Characteristics” for
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.1 EXTERNAL SUPERVISORY CIRCUIT
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.3.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle, and the reset vector fetch
will commence.
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control register (RCON<6>) is set to indicate
the software Reset.
6.5 Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
Reset Control register (RCON<4>) is set to indicate
the Watchdog Reset. Refer to Section 19.4
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
6.6 Trap Conflict Reset
If a lower-priority hard trap occurs while a
higher-priority trap is being processed, a hard trap
conflict Reset occurs. The hard traps include
exceptions of priority level 13 through level 15,
inclusive. The address error (level 13) and oscillator
error (level 14) traps fall into this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on trap conflict Resets.
© 2007-2011 Microchip Technology Inc.
DS70289H-page 61