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PIC24HJ16GP304-E Datasheet, PDF (258/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers | |||
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PIC24HJ32GP202/204 AND PIC24HJ16GP304
TABLE 24-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 15.0 âInter-Integrated
Circuit (I2Câ¢)â
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
⢠15.3 âI2C Interruptsâ
⢠15.4 âBaud Rate Generatorâ (retained Figure 15-1: I2C Block Diagram)
⢠15.5 âI2C Module Addressesâ
⢠15.6 âSlave Address Maskingâ
⢠15.7 âIPMI Supportâ
⢠15.8 âGeneral Call Address Supportâ
⢠15.9 âAutomatic Clock Stretchâ
⢠15.10 âSoftware Controlled Clock Stretching (STREN = 1)â
⢠15.11 âSlope Controlâ
⢠15.12 âClock Arbitrationâ
⢠15.13 âMulti-Master Communication, Bus Collision, and Bus Arbitrationâ
⢠15.14 âPeripheral Pin Select Limitationsâ
Section 16.0 âUniversal
Removed the following sections, which are now available in the related
Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual:
(UART)â
⢠16.1 âUART Baud Rate Generatorâ
⢠16.2 âTransmitting in 8-bit Data Modeâ
⢠16.3 âTransmitting in 9-bit Data Modeâ
⢠16.4 âBreak and Sync Transmit Sequenceâ
⢠16.5 âReceiving in 8-bit or 9-bit Data Modeâ
⢠16.6 âFlow Control Using UxCTS and UxRTS Pinsâ
⢠16.7 âInfrared Supportâ
Section 17.0 â10-bit/12-bit Analog-
to-Digital Converter (ADC)â
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 16-2).
Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2:
ADC Transfer Function (10-bit Example).
Added ADC1 Module Block Diagram for PIC24HFJ16GP304 and
PIC24HJ32GP204 Devices (Figure 17-1) and ADC1 Module Block Diagram
FOR PIC24HJ32GP202 Devices (Figure 17-2).
Added Note 2 to Figure 17-3: ADC Conversion Clock Period Block Diagram.
Added device-specific information to Note 1 in the ADC1 Input Scan Select
Register Low (see Register 17-6), and updated the default bit value for bits
12-10 (CSS12-CSS10) from U-0 to R/W-0.
Added device-specific information to Note 1 in the ADC1 Port Configuration
Register Low (see Register 17-7), and updated the default bit value for bits
12-10 (PCFG12-PCFG10) from U-0 to R/W-0.
DS70289H-page 258
© 2007-2011 Microchip Technology Inc.
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