PIC24HJ16GP304-E Datasheet, PDF (60/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
TABLE 6-2: OSCILLATOR PARAMETERS
Symbol
Parameter
VPOR
TPOR
VBOR
TBOR
TPWRT
TFSCM
POR threshold
POR extension time
BOR threshold
BOR extension time
Programmable power-up time delay
Fail-Safe Clock Monitor Delay
Value
1.8V nominal
30 μs maximum
2.5V nominal
100 μs maximum
0-128 ms nominal
900 μs maximum
Note:
When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all operating parameters within
specification.
6.2 Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay TPOR
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 22.0 “Electrical Characteristics” for details.
The POR status bit in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
6.2.1
Brown-out Reset (BOR) and
Power-up Timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses
VBOR threshold and the delay TBOR has elapsed. The
delay TBOR ensures the voltage regulator output
becomes stable.
The BOR status bit in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the Power-on Reset Timer Value Select
(FPWRT<2:0>) bits in the POR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 19.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
DS70289H-page 60
© 2007-2011 Microchip Technology Inc.