PIC24HJ16GP304-E Datasheet, PDF (268/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
Instruction Set
Overview ................................................................... 181
Summary................................................................... 179
Instruction-Based Power-Saving Modes ............................. 99
Idle ............................................................................ 100
Sleep ........................................................................... 99
Internal RC Oscillator
Use with WDT ........................................................... 176
Internet Address................................................................ 271
Interrupt Control and Status Registers................................ 66
IECx ............................................................................ 66
IFSx............................................................................. 66
INTCON1 .................................................................... 66
INTCON2 .................................................................... 66
IPCx ............................................................................ 66
Interrupt Setup Procedures ................................................. 88
Initialization ................................................................. 88
Interrupt Disable.......................................................... 88
Interrupt Service Routine ............................................ 88
Trap Service Routine .................................................. 88
Interrupt Vector Table (IVT) ................................................ 63
Interrupts Coincident with Power Save Instructions.......... 100
J
JTAG Boundary Scan Interface ........................................ 171
M
Memory Organization.......................................................... 27
Microchip Internet Web Site .............................................. 271
MPLAB ASM30 Assembler, Linker, Librarian ................... 188
MPLAB Integrated Development Environment Software .. 187
MPLAB PM3 Device Programmer..................................... 190
MPLAB REAL ICE In-Circuit Emulator System................. 189
MPLINK Object Linker/MPLIB Object Librarian ................ 188
Multi-bit Data Shifter............................................................ 26
N
NVM Module
Register Map............................................................... 41
O
Open-Drain Configuration ................................................. 104
Output Compare................................................................ 133
Registers ................................................................... 135
P
Packaging ......................................................................... 245
Details ....................................................................... 247
Marking ............................................................. 245, 246
Peripheral Module Disable (PMD)..................................... 100
Pinout I/O Descriptions (table) ............................................ 13
PMD Module
Register Map............................................................... 41
PORTA
Register Map............................................................... 40
PORTB
Register Map............................................................... 40
Power-on Reset (POR) ....................................................... 60
Power-Saving Features....................................................... 99
Clock Frequency and Switching.................................. 99
Program Address Space ..................................................... 27
Construction ................................................................ 44
Data Access from Program Memory Using Program
Space Visibility.................................................... 47
Data Access from Program Memory Using Table Instruc-
tions .................................................................... 46
Data Access from, Address Generation ..................... 45
Memory Map............................................................... 27
Table Read Instructions
TBLRDH ............................................................. 46
TBLRDL.............................................................. 46
Visibility Operation ...................................................... 47
Program Memory
Interrupt Vector ........................................................... 28
Organization ............................................................... 28
Reset Vector ............................................................... 28
R
Reader Response............................................................. 272
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 167
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 165
AD1CON1 (ADC1 Control 1) .................................... 161
AD1CON2 (ADC1 Control 2) .................................... 163
AD1CON3 (ADC1 Control 3) .................................... 164
AD1CSSL (ADC1 Input Scan Select Low)................ 169
AD1PCFGL (ADC1 Port Configuration Low) ............ 169
CLKDIV (Clock Divisor) .............................................. 94
CORCON (Core Control) ...................................... 25, 68
I2CxCON (I2Cx Control) ........................................... 145
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 149
I2CxSTAT (I2Cx Status) ........................................... 147
ICxCON (Input Capture x Control)............................ 132
IEC0 (Interrupt Enable Control 0) ......................... 75, 78
IEC1 (Interrupt Enable Control 1) ............................... 77
IFS0 (Interrupt Flag Status 0) ..................................... 71
IFS1 (Interrupt Flag Status 1) ..................................... 73
IFS4 (Interrupt Flag Status 4) ..................................... 74
INTCON1 (Interrupt Control 1).................................... 69
INTCON2 (Interrupt Control 2).................................... 70
INTTREG Interrupt Control and Status Register ........ 87
IPC0 (Interrupt Priority Control 0) ............................... 79
IPC1 (Interrupt Priority Control 1) ............................... 80
IPC16 (Interrupt Priority Control 16) ........................... 86
IPC2 (Interrupt Priority Control 2) ............................... 81
IPC3 (Interrupt Priority Control 3) ............................... 82
IPC4 (Interrupt Priority Control 4) ............................... 83
IPC5 (Interrupt Priority Control 5) ............................... 84
IPC7 (Interrupt Priority Control 7) ............................... 85
NVMCOM (Flash Memory Control)....................... 51, 52
OCxCON (Output Compare x Control) ..................... 135
OSCCON (Oscillator Control) ..................................... 92
OSCTUN (FRC Oscillator Tuning).............................. 96
PLLFBD (PLL Feedback Divisor)................................ 95
PMD1 (Peripheral Module Disable Control
Register 1) ........................................................ 101
PMD2 (Peripheral Module Disable Control
Register 2) ........................................................ 102
RCON (Reset Control)................................................ 56
SPIxCON1 (SPIx Control 1)...................................... 139
SPIxCON2 (SPIx Control 2)...................................... 141
SPIxSTAT (SPIx Status and Control) ....................... 138
SR (CPU Status)................................................... 24, 67
T1CON (Timer1 Control) .......................................... 124
TxCON (T2CON, T4CON, T6CON or
T8CON Control)................................................ 128
TyCON (T3CON, T5CON, T7CON or
T9CON Control)................................................ 129
UxMODE (UARTx Mode).......................................... 152
UxSTA (UARTx Status and Control)......................... 154
Reset
Illegal Opcode....................................................... 55, 62
DS70289H-page 268
© 2007-2011 Microchip Technology Inc.