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PIC24HJ16GP304-E Datasheet, PDF (55/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers | |||
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PIC24HJ32GP202/204 AND PIC24HJ16GP304
6.0 RESETS
Note 1: This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 family of devices. It is
not intended to be a comprehensive ref-
erence source. To complement the infor-
mation in this data sheet, refer to
âSection 8. Resetâ (DS70192) of the
âdsPIC33F/PIC24H Family Reference
Manualâ, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 âMemory Organizationâ in
this data sheet for device-specific register
and bit information.
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
⢠POR: Power-on Reset
⢠BOR: Brown-out Reset
⢠MCLR: Master Clear Pin Reset
⢠SWR: RESET Instruction
⢠WDTO: Watchdog Timer Reset
⢠CM: Configuration Mismatch Reset
⢠TRAPR: Trap Conflict Reset
⢠IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 3.0 âCPUâ of this manual for
register Reset states.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
MCLR
Glitch Filter
WDT
Module
Sleep or Idle
Internal
Regulator
VDD
BOR
VDD Rise POR
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
SYSRST
© 2007-2011 Microchip Technology Inc.
DS70289H-page 55
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