PIC24HJ16GP304-E Datasheet, PDF (175/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
19.2 On-Chip Voltage Regulator
All of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices in the PIC24HJ32GP202/204 and
PIC24HJ16GP304 family incorporate an on-chip regu-
lator that allows the device to run its core logic from
VDD.
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 19-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 22-13 located in Section 22.1
“DC Characteristics”.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
On a POR, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 19-1:
3.3V
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR⁽¹⁾
PIC24H
CEFC
10 µF
VDD
VCAP
VSS
19.3 Brown-Out Reset (BOR)
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the
regulated voltage VCAP. The main purpose of the BOR
module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If TPWRT
= 0 and a crystal oscillator is being used, a nominal
delay of TFSCM = 100 is applied. The total delay in this
case is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle mode and resets the
device in case VDD falls below the BOR threshold
voltage.
Note 1:
2:
3:
These are typical operating voltages. Refer to
Table 22-13 located in Section 22.1 “DC
Characteristics” for the full operating ranges
of VDD and VCAP.
It is important for the low-ESR capacitor to be
placed as close as possible to the VCAP pin.
Typical VCAP pin voltage = 2.5V when VDD ≥
VDDMIN.
© 2007-2011 Microchip Technology Inc.
DS70289H-page 175