PIC24HJ16GP304-E Datasheet, PDF (50/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
5.2 RTSP Operation
The Flash program memory array is organized into
rows of 64 instructions or 192 bytes. RTSP allows the
user application to erase a page of memory, which con-
sists of eight rows (512 instructions) at a time, and to
program one row or one word at a time. The 8-row
erase pages and single row write rows are
edge-aligned from the beginning of program memory,
on boundaries of 1536 bytes and 192 bytes,
respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All table write operations are single-word writes (two
instruction cycles) because only the buffers are written.
A programming cycle is required for programming each
row.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 22-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see Table 22-12).
EQUATION 5-1: PROGRAMMING TIME
7---.--3---7-----M^-----H^----z^----×^------(^--F^----R^----C^-----A^----c^--c^---u^---r^--Ta---c^---y^---)^---%------×^------(^--F^----R^----C^-----T^---u^---n^---i^--n^---g^----)^--%---
For example, if the device is operating at +125° C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see Register 8-4) are set to ‘b111111, the
minimum row write time is equal to Equation 5-2.
EQUATION 5-2: MINIMUM ROW WRITE
TIME
T_RW = _{7----.-3---7-----M}-----_H----_z----_×------₍-¹-1--¹---⁰₊---⁶--0-⁴--.-0-^C--5--^y--₎-^c--_×^l--^e---^s-₍--1-----_–----0---.--0---0---3---7---5---₎-= 1.435ms
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3: MAXIMUM ROW WRITE
TIME
T_RW
=
--------------------------------¹---¹---⁰---⁶---⁴-----^C----^y---^c--^l--^e---^s--------------------------------
7.37 MHz × (1 – 0.05) × (1 – 0.00375)
= 1.586ms
Setting the WR bit (NVMCON<15>) starts the
operaion, and the WR bit is automatically cleared when
the operation is finished.
5.4 Control Registers
The two SFRs that are used to read and write the
program Flash memory are:
• NVMCON: Flash Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
The NVMCON register (Register 5-1) controls which
blocks need to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 5-2) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must
consecutively write 0x55 and 0xAA to the NVMKEY
register. Refer to Section 5.3 “Programming
Operations” for further details.
DS70289H-page 50
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