PIC24HJ16GP304-E Datasheet, PDF (21/274 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

PIC24HJ32GP202/204 AND PIC24HJ16GP304
3.0 CPU
Note 1: This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 family of devices.
However, it is not intended to be a com-
prehensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 2. CPU” (DS70204) of
the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
CPU modules have a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and
addressing modes. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space. The
actual amount of program memory implemented varies
by device. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double word move
(MOV.D) instruction and the table instructions.
Overhead-free, single-cycle program loop constructs
are supported using the REPEAT instruction, which is
interruptible at any time.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices have sixteen, 16-bit working registers in the
programmer’s model. Each of the working registers can
serve as a data, address or address offset register. The
16th working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
The instruction set includes many addressing modes
and is designed for optimum C compiler efficiency. For
most instructions, the devices are capable of executing
a data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1. The
programmer’s model for the PIC24HJ32GP202/204
and PIC24HJ16GP304 is shown in Figure 3-2.
3.1 Data Addressing Overview
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K pro-
gram word boundary defined by the 8-bit Program Space
Visibility Page register (PSVPAG). The program to data
space mapping feature lets any instruction access pro-
gram space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but this
may be used as general purpose RAM.
3.2 Special MCU Features
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices feature a 17-bit by 17-bit, single-cycle
multiplier. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication makes
mixed-sign multiplication possible.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices support 16/16 and 32/16 integer divide
operations. All divide instructions are iterative
operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during
any of those 19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
© 2007-2011 Microchip Technology Inc.
DS70289H-page 21