PIC16LF720_11 Datasheet, PDF (97/244 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

13.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
13.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 13.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
13.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
PIC16(L)F720/721
13.5 Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 gate count
enable.
Timer1 gate can also be driven by multiple selectable
sources.
13.5.1 TIMER1 GATE COUNT ENABLE
The Timer1 gate is enabled by setting the TMR1GE bit
of the T1GCON register. The polarity of the Timer1 gate
is configured using the T1GPOL bit of the T1GCON
register.
When Timer1 Gate (T1G) input is active, Timer1 will
increment on the rising edge of the Timer1 clock
source. When Timer1 gate input is inactive, no
incrementing will occur and Timer1 will hold the current
count. See Figure 13-3 for timing details.
TABLE 13-3: TIMER1 GATE ENABLE
SELECTIONS
T1CLK T1GPOL T1G Timer1 Operation

0
0 Counts

0
1 Holds Count

1
0 Holds Count

1
1 Counts
13.5.2 TIMER1 GATE SOURCE
SELECTION
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 13-4: TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Source
00 Timer1 Gate Pin
01 Overflow of Timer0
(TMR0 increments from FFh to 00h)
10 Timer2 match PR2
(TMR2 increments to match PR2)
11 Count Enabled by WDT Overflow
(Watchdog Time-out interval expired)
 2011 Microchip Technology Inc.
Preliminary
DS41430B-page 97