PIC16LF720_11 Datasheet, PDF (83/244 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F720/721
9.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 9-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 9-3. The maximum recommended
impedance for analog sources is 10 k. As the
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To
calculate the minimum acquisition time, Equation 9-1
may be used. This equation assumes that 1/2 LSb error
is used (256 steps for the ADC). The 1/2 LSb error is
the maximum error allowed for the ADC to meet its
specified resolution. It is noted that if the device is
operated at or below 2.0V VDD with the FRC clock
selected for the ADC and if the analog input changes
by more than 1 or 2 LSBs from the previous
conversion, then the use of at least 16 s TACQ time is
recommended.
EQUATION 9-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
Note: TCOFF is zero for temperatures below 25 degrees C.
The value for TC can be approximated with the following equations:
V
A
P
P
LI
E
D


1
–
^{---2---n----+--1--1--}^----–^{----1--}
=
VCHOLD
;[1] VCHOLD charged to within 1/2 lsb

VAPPLIED1
–
e^{–-R---T--C-C--}
=
VCHOLD


;[2] VCHOLD charge response to VAPPLIED

VAPPLIED1
–
e^{–-R---T-C--c-}


=
V
A
P
P
L
I
E
D


1
–
^{---2---n----+--1--1--}^----–^{----1--}
;combining [1] and [2]
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/511)
= –20pF1k + 7k + 10k ln(0.001957)
= 2.25µs
Therefore:
TACQ = 2µs + 2.25µs + 50°C- 25°C0.05µs/°C
= 5.5µs
 2011 Microchip Technology Inc.
Preliminary
DS41430B-page 83