PIC16LF720_11 Datasheet, PDF (112/244 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F720/721
15.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 module may:
• Toggle the CCP1 output
• Set the CCP1 output
• Clear the CCP1 output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register.
All Compare modes can generate an interrupt.
FIGURE 15-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1CON<3:0>
Mode Select
CCP1
Set CCP1IF Interrupt Flag
4 ^(PIR1)
CCPR1H CCPR1L
Q S _Output
R ^Logic
Match
Comparator
TRIS
Output Enable
TMR1H TMR1L
Special Event Trigger
Special Event Trigger will:
• Clear TMR1H and TMR1L registers.
• NOT set interrupt flag bit TMR1IF of the PIR1 register.
• Set the GO/DONE bit to start the ADC conversion.
15.2.1 CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
15.2.2 TIMER1 MODE SELECTION
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. For the Compare operation of the
TMR1 register to the CCPR1 register to
occur, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
15.2.3 SOFTWARE INTERRUPT MODE
When Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1IF bit in the PIR1
register is set and the CCP1 module does not assert
control of the CCP1 pin (refer to the CCP1CON
register).
15.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode (refer to the CCP1CON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
15.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
DS41430B-page 112
Preliminary
 2011 Microchip Technology Inc.