PIC16LF720_11 Datasheet, PDF (149/244 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

17.2 I²C Mode
The SSP module, in I²C mode, implements all slave
functions except general call support. It provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the I²C Standard mode
specifications:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• Start and Stop bit interrupts enabled to support
firmware Master mode
• Address masking
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin’s data direction bits as inputs in
the appropriate TRIS register. Upon enabling I²C
mode, the I²C slew rate limiters in the I/O pads are
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
Data is sampled on the rising edge and shifted out on
the falling edge of the clock. This ensures that the SDA
signal is valid during the SCL high time. The SCL clock
input must have minimum high and low times for proper
operation. Refer to Section 23.0 “Electrical
Specifications”.
FIGURE 17-7:
I²C™ MODE BLOCK
DIAGRAM
Read
Internal
Data Bus
Write
SCL
SDA
SSPBUF Reg
Shift
Clock
SSPSR Reg
MSb
LSb
SSPMSK Reg
Match Detect
SSPADD Reg
Addr Match
Start and
Stop bit Detect
PIC16(L)F720/721
FIGURE 17-8:
TYPICAL I²C™
CONNECTIONS
VDD VDD
Master
SDA
SCL
Slave 1
SDA
SCL
Slave 2
SDA
SCL
(optional)
The SSP module has six registers for I²C operation.
They are:
• SSP Control (SSPCON) register
• SSP Status (SSPSTAT) register
• Serial Receive/Transmit Buffer (SSPBUF) register
• SSP Shift Register (SSPSR), not directly
accessible
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
17.2.1 HARDWARE SETUP
Selection of I²C mode, with the SSPEN bit of the
SSPCON register set, forces the SCL and SDA pins to
be open drain, provided these pins are programmed as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the output data,
when required, such as for Acknowledge and slave-
transmitter sequences.
Note:
Pull-up resistors must be provided
externally to the SCL and SDA pins for
proper operation of the I²C module.
 2011 Microchip Technology Inc.
Preliminary
DS41430B-page 149