PIC16LF720_11 Datasheet, PDF (157/244 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F720/721
17.2.10 CLOCK SYNCHRONIZATION
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. Therefore, the CKP bit will not
stretch the SCL line until an external I²C master device
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I²C bus have released SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (Figure 17-14).
17.2.11 SLEEP OPERATION
While in Sleep mode, the I²C module can receive
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
FIGURE 17-14: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
CKP
WR
SSPCON
DX
Master device
asserts clock
Master device
de-asserts clock
DX-1
 2011 Microchip Technology Inc.
Preliminary
DS41430B-page 157