PIC16F737-I Datasheet, PDF (93/276 Pages) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

9.6 PWM Mode (PWM)
In Pulse-Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 9.6.3 “Setup
for PWM Operation”.
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
CCP1CON<5:4>
CCPR1L
CCPR1H (Slave)
Comparator
R
TMR2
(Note 1)
Comparator
PR2
(1)
S
Clear Timer,
CCP1 pin and
latch D.C.
Q
RC2/CCP1
TRISC<2>
Note 1: The 8-bit timer is concatenated with the 2-bit
internal Q clock or 2 bits of the prescaler to create
the 10-bit time base.
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 9-4:
PWM OUTPUT
TMR2
Reset
Period
TMR2
Reset
PIC16F7X7
9.6.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 9-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 9.4
“Capture Mode”) is not used in the deter-
mination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
9.6.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 9-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>)•
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
 2004 Microchip Technology Inc.
DS30498C-page 91