PIC16F737-I Datasheet, PDF (162/276 Pages) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC16F7X7
12.7 A/D Operation During Sleep
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRESH register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction immediately follows the
instruction that sets the GO/DONE bit.
12.8 Effects of a Reset
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRESH register will contain unknown data after
a Power-on Reset.
12.9 Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRESH
to the desired location). The appropriate analog input
channel must be selected and an appropriate acquisi-
tion time should pass before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
TABLE 12-2: SUMMARY OF A/D REGISTERS
Address Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh, INTCON
10Bh, 18Bh
0Ch
PIR1
GIE
PSPIF⁽¹⁾
PEIE TMR0IE
ADIF RCIF
INT0IE
TXIF
RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh
PIR2
OSFIF CMIF LVDIF
—
BCLIF
—
CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch
PIE1
PSPIE⁽¹⁾ ADIE RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh
PIE2
OSFIE CMIE LVDIE
—
BCLIE
—
CCP3IE CCP2IE 000- 0-00 000- 0-00
1Eh
ADRESH A/D Result Register High Byte
xxxx xxxx uuuu uuuu
1Fh
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh
ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 000 0000 0000
05h
PORTA
RA7
RA6 RA5
RA4
RA3
RA2
RA1 RA0 xx0x 0000 uu0u 0000
85h
TRISA PORTA Data Direction Register
1111 1111 1111 1111
09h
PORTE⁽²⁾ —
—
—
—
RE3⁽³⁾ RE2
RE1 RE0 ---- x000 ---- x000
89h
TRISE⁽²⁾
IBF
OBF IBOV PSPMODE —⁽³⁾ PORTE Data Direction bits 0000 1111 0000 1111
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
These registers are reserved on the PIC16F737/767 devices.
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
DS30498C-page 160
 2004 Microchip Technology Inc.