PIC16F737-I Datasheet, PDF (193/276 Pages) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC16F7X7
15.18.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
FIGURE 15-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC1
CLKO⁽⁴⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽²⁾
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC
Inst(PC) = Sleep
Inst(PC – 1)
Processor in
Sleep
PC + 1
Inst(PC + 1)
Sleep
PC + 2
Interrupt Latency
(Note 2)
PC + 2
Inst(PC + 2)
Inst(PC + 1)
PC + 2
0004h
Inst(0004h)
Dummy Cycle Dummy Cycle
0005h
Inst(0005h)
Inst(0004h)
Note 1:
2:
3:
4:
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
CLKO is not available in these oscillator modes but shown here for timing reference.
 2004 Microchip Technology Inc.
DS30498C-page 191