PIC16F737-I Datasheet, PDF(22/276 Page) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC16F737-I Datasheet, PDF (22/276 Pages) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC16F7X7

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Details

POR, BOR on page

Bank 2

100h(4) INDF

101h TMR0

102h(4) PCL

103h(4) STATUS

104h(4) FSR

105h WDTCON

106h PORTB

107h

â

108h

â

109h LVDCON

10Ah(1,4) PCLATH

10Bh(4) INTCON

10Ch PMDATA

10Dh PMADR

10Eh PMDATH

10Fh PMADRH

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000

Timer0 Module Register

xxxx xxxx

Program Counter (PC) Least Significant Byte

0000 0000

IRP

RP1

RP0

TO

PD

Z

DC

C 0001 1xxx

Indirect Data Memory Address Pointer

xxxx xxxx

â

â

â

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

Unimplemented

â

Unimplemented

â

â

â

IRVST

LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101

â

â

â Write Buffer for the upper 5 bits of the Program Counter ---0 0000

GIE

PEIE TMR0IE INT0IE

RBIE TMR0IF INT0IF RBIF 0000 000x

EEPROM Data Register Low Byte

xxxx xxxx

EEPROM Address Register Low Byte

xxxx xxxx

â

â EEPROM Data Register High Byte

--xx xxxx

â

â

â

â

EEPROM Address Register High Byte

---- xxxx

30, 180

76, 180

29, 180

21, 180

30, 180

187

64, 180

â

â

176

23, 180

25, 180

32, 181

32, 181

32, 181

32, 181

Bank 3

180h(4) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180

181h OPTION_REG RBPU INTEDG T0CS

T0SE

182h(4) PCL

Program Counter (PC) Least Significant Byte

PSA

PS2

PS1

PS0 1111 1111 22, 180

0000 0000 29, 180

183h(4) STATUS

184h(4) FSR

IRP

RP1

RP0

TO

Indirect Data Memory Address Pointer

PD

Z

DC

C 0001 1xxx 21, 180

xxxx xxxx 30, 180

185h

â

Unimplemented

â

â

186h TRISB

PORTB Data Direction Register

1111 1111 64, 181

187h

â

Unimplemented

â

â

188h

â

Unimplemented

â

â

189h

â

18Ah(1,4) PCLATH

18Bh(4) INTCON

18Ch PMCON1

Unimplemented

â

â

GIE

PEIE

r(6)

â

â

TMR0IE

â

Write Buffer for the upper 5 bits of the Program Counter

INT0IE

RBIE TMR0IF INT0IF RBIF

â

â

â

â

RD

â

---0 0000

0000 000x

1--- ---0

â

23, 180

25, 180

32, 181

18Dh

â

Reserved, maintain clear

â

â

18Eh

â

Reserved, maintain clear

â

â

18Fh

â

Reserved, maintain clear

â

â

Legend: x = unknown, u = unchanged, q = value depends on condition, â = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents

are transferred to the upper byte of the program counter during branches (CALL or GOTO).

2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

4: These registers can be addressed from any bank.

5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as â0â.

6: This bit always reads as a â1â.

7: OSCCON<OSTS> bit resets to â0â with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.

8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read â1â.

DS30498C-page 20

ï£© 2004 Microchip Technology Inc.

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