PIC16F737-I Datasheet, PDF(103/276 Page) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC16F737-I Datasheet, PDF (103/276 Pages) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

◁

PIC16F7X7

10.3.8 SLEEP OPERATION

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from Sleep. After the device returns to

normal mode, the module will continue to transmit/

receive data.

In Slave mode, the SPI Transmit/Receive Shift register

operates asynchronously to the device. This allows the

device to be placed in Sleep mode and data to be

shifted into the SPI Transmit/Receive Shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled, will wake the device

from Sleep.

10.3.9 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

10.3.10 BUS MODE COMPATIBILITY

Table 10-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 10-1: SPIâ¢ BUS MODES

Standard SPIâ¢

Mode Terminology

Control Bits State

CKP

CKE

0, 0

0

1

0, 1

0

0

1, 0

1

1

1, 1

1

0

There is also an SMP bit which controls when the data

is sampled.

TABLE 10-2: REGISTERS ASSOCIATED WITH SPIâ¢ OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

PIR1

PIE1

GIE/GIEH PEIE/GIEL

PSPIF(1)

ADIF

PSPIE(1)

ADIE

TMR0IE

RCIF

RCIE

INT0IE

TXIF

TXIE

RBIE

SSPIF

SSPIE

TMR0IF

CCP1IF

CCP1IE

INT0IF

TMR2IF

TMR2IE

RBIF

TMR1IF

TMR1IE

0000 000x 0000 000u

0000 0000 0000 0000

0000 0000 0000 0000

TRISC PORTC Data Direction Register

1111 1111 1111 1111

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

TRISA PORTA Data Direction Register

1111 1111 1111 1111

SSPSTAT SMP

CKE

D/A

P

S

R/W

UA

BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, â = unimplemented, read as â0â. Shaded cells are not used by the MSSP in SPIâ¢ mode.

Note 1: The PSPIF and PSPIE bits are reserved on 28-pin devices; always maintain these bits clear.

ï£© 2004 Microchip Technology Inc.

DS30498C-page 101

▷