PIC16F737-I Datasheet, PDF (67/276 Pages) Microchip Technology – 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

5.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 5-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings and to Section 16.1 “Read-Modify-
Write Operations” for additional information on
read-modify-write operations.
FIGURE 5-16:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5> PINS
Port/Peripheral Select⁽²⁾
Peripheral Data Out
0
Data Bus
D
Q
WR
Port
CK Q 1
Data Latch
WR
TRIS
D
Q
CK Q
TRIS Latch
RD
TRIS
Peripheral
OE⁽³⁾
Q
VDD
P _I/O
pin⁽¹⁾
N
VSS
Schmitt
Trigger
D
RD
EN
Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port
data and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
PIC16F7X7
FIGURE 5-17:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3> PINS
Port/Peripheral Select⁽²⁾
Peripheral Data Out
Data Bus
WR
Port
D
Q
CK Q
Data Latch
WR
TRIS
RD
TRIS
D
Q
CK Q
TRIS Latch
Peripheral
OE⁽³⁾
RD
Port
SSPl Input
0
VDD
P
I/O
1
pin⁽¹⁾
N
Vss
Schmitt
Trigger
QD
EN
Schmitt
Trigger
with
SMBus
0 Levels
1
CKE
SSPSTAT<6>
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data
and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
 2004 Microchip Technology Inc.
DS30498C-page 65