LAN8820 Datasheet, PDF (9/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
TABLE 2-5: JTAG PINS
Num Pins
Name
1
JTAG Test
Data Out
1
JTAG Test
Data Input
1
JTAG Test
Clock
1
JTAG Test
Mode Select
Symbol
TDO
TDI
TCK
TMS
TABLE 2-6: MISCELLANEOUS PINS
Num Pins
Name
Crystal Input
Symbol
XI
1
1
Crystal
Output
XO
1
System Reset
nRESET
1
Interrupt
IRQ
Request
Hardware
1
Power Down
1
No Connect
HPD
NC
Buffer
Type
O8
Description
JTAG (IEEE 1149.1) data output.
IS
(PU)
IS
(PD)
IS
(PU)
JTAG (IEEE 1149.1) data input.
Note: When not used, tie this pin to VDD25IO.
JTAG (IEEE 1149.1) test clock.
Note: When not used, tie this pin to VSS.
JTAG (IEEE 1149.1) test mode select.
Note: When not used, tie this pin to VDD25IO.
Buffer
Type
ICLK
OCLK
Description
External 25 MHz crystal input.
Note:
This pin can also be driven by a 25 MHz
single-ended clock oscillator. When this
method is used, XO should be left
unconnected. Refer to Section 5.6,
"Clock Circuit," on page 75 for additional
information.
External 25 MHz crystal output.
IS
(PU)
O6
IS
(PD)
-
This active-low pin allows external hardware to
reset the device.
Programmable interrupt request.
Note: When used, this pin requires an
external 4.7K pull-up resistor.
When asserted, this pin places the device into
Hardware Power Down (HPD) mode. Refer to
Section 3.7.3, "Hardware Power-Down," on
page 23 for additional information.
This pin must be left floating for normal device
operation.
 2009-2015 Microchip Technology Inc.
DS00001871B-page 9