LAN8820 Datasheet, PDF (69/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
5.5.5 RGMII TIMING
This section specifies the RGMII interface transmit and receive timing. The RGMII interface supports the independent
enabling/disabling of the PHY TXC and RXC delays, each with unique timing properties. These timing are reflected in
the following sub-sections. Please refer to Section 3.3, "RGMII Interface," on page 18 for additional details.
Note: All RGMII timing specifications assume a point-to-point test circuit as defined in Figure 3 of the RGMII spec-
ification 1.3.
5.5.5.1 PHY TXC Delay Enabled Timing
FIGURE 5-5:
RGMII PHY TXC DELAY ENABLED TIMING
TXC
TXD[3:0]
TXCTRL
t_txc
t_clkh t_clkl
t_setup
t_setup
t_hold
TXD
[3:0]
TXD
[7:4]
t_hold
TXEN
TXER
t_setup
t_setup
t_hold
t_hold
TABLE 5-14: RGMII PHY TXC DELAY ENABLED TIMING VALUES
Symbol
t_txc
t_clkh
t_clkl
t_setup
t_hold
Description
TXC period
TXC high time
TXC low time
TXD[3:0], TXCTRL setup time to edge of TXC
TXD[3:0], TXCTRL hold time after edge of TXC
Min
Note 5-1
Note 5-4
Note 5-4
-0.9
2.7
Typ
Note 5-2
50
50
Max
Note 5-3
Note 5-5
Note 5-5
Units
ns
%
%
ns
ns
Note 5-1
Note 5-2
Note 5-3
Note 5-4
Note 5-5
7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.
Minimum limits are non-sustainable long term.
8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.
Maximum limits are non-sustainable long term.
45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.
55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.
 2009-2015 Microchip Technology Inc.
DS00001871B-page 69