LAN8820 Datasheet, PDF (71/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
5.5.5.3 PHY RXC Delay Enabled Timing
FIGURE 5-7:
RGMII PHY RXC DELAY ENABLED TIMING
RXC
RXD[3:0]
RXCTRL
t_setup
t_setup
t_rxc
t_clkh t_clkl
t_hold
RXD
[3:0]
t_hold
t_setup
RXD
[7:4]
t_setup
RXDV
RXER
t_hold
t_hold
TABLE 5-16: RGMII PHY RXC DELAY ENABLED TIMING VALUES
Symbol
t_rxc
t_clkh
t_clkl
t_setup
t_hold
Description
RXC period
RXC high time
RXC low time
RXD[3:0], RXCTRL output setup from edge of
RXC
RXD[3:0], RXCTRL output hold from edge of
RXC
Min
Note 5-11
Note 5-14
Note 5-14
1.2
Typ
Note 5-12
50
50
Max
Note 5-13
Note 5-15
Note 5-15
Units
ns
%
%
ns
1.2
ns
Note 5-11
Note 5-12
Note 5-13
Note 5-14
Note 5-15
7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.
Minimum limits are non-sustainable long term.
8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.
Maximum limits are non-sustainable long term.
45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.
55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.
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DS00001871B-page 71