LAN8820 Datasheet, PDF (8/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
TABLE 2-3: LED & CONFIGURATION PINS (CONTINUED)
Num
Pins
Name
Symbols
Buffer
Type
Description
Configuration
Input 2
1
Configuration
Input 3
1
CONFIG2
CONFIG3
IS
(PD)
IS
(PD)
This pin sets the MOD[1:0] bits of the Extended
Mode Control/Status Register on reset or power-
up. It must be connected to VSS, 100_LED,
1000_LED, or VDD25IO. Refer to Section 3.8.1.2,
"CONFIG[3:0] Configuration Pins," on page 24 for
additional information.
This pin sets the MOD[3] bit of the Extended Mode
Control/Status Register on reset or power-up. It
must be connected to 1000_LED. Refer to Section
3.8.1.2, "CONFIG[3:0] Configuration Pins," on
page 24 for additional information.
Note 2-2
Configuration strap values are latched on hardware reset. Configuration straps are identified by an
underlined symbol name. Signals that function as configuration straps must be augmented with an
external resistor when connected to a load. Refer to Section 3.8, "Configuration," on page 23 for
additional information.
TABLE 2-4: ETHERNET PINS
Num Pins
Name
Ethernet TX/
1
RX Positive
Channel 0
Ethernet TX/
1
RX Negative
Channel 0
Ethernet TX/
1
RX Positive
Channel 1
Ethernet TX/
1
RX Negative
Channel 1
Ethernet TX/
1
RX Positive
Channel 2
Ethernet TX/
1
RX Negative
Channel 2
Ethernet TX/
1
RX Positive
Channel 3
Ethernet TX/
1
RX Negative
Channel 3
1
External PHY
Bias Resistor
Symbol
TR0P
TR0N
TR1P
TR1N
TR2P
TR2N
TR3P
TR3N
ETHRBIAS
Buffer
Type
AIO
Description
Transmit/Receive Positive Channel 0.
AIO
Transmit/Receive Negative Channel 0.
AIO
Transmit/Receive Positive Channel 1.
AIO
Transmit/Receive Negative Channel 1.
AIO
Transmit/Receive Positive Channel 2.
AIO
Transmit/Receive Negative Channel 2.
AIO
Transmit/Receive Positive Channel 3.
AIO
Transmit/Receive Negative Channel 3.
AI
Used for the internal bias circuits. Connect to an
external 8.06K 1.0% resistor to ground.
DS00001871B-page 8
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